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Items where Author is "Blaquière, Yves"

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Number of items: 16.

2023

Bensalem, H., Blaquière, Y., & Savaria, Y. (2023). An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform. IEEE Transactions on Circuits and Systems II: Express Briefs, 70(3), 1144-1148. External link

2018

Darvishi, M., Audet, Y., & Blaquière, Y. (2018). Delay monitor circuit and delay change measurement due to SEU in SRAM-based FPGA. IEEE Transactions on Nuclear Science, 65(5), 1153-1160. External link

Berrima, S., Blaquière, Y., & Savaria, Y. (2018). Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integration, 62, 159-169. External link

Lepercq, É., Blaquière, Y., & Savaria, Y. (2018). A pattern-based routing algorithm for a novel electronic system prototyping platform. Integration, 62, 224-237. External link

2013

Baratli, K., Lakhssassi, A., Blaquière, Y., & Savaria, Y. (2013, June). A netlist pruning tool for an electronic system prototyping platform [Paper]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. External link

2012

Thibeault, C., Pichette, S., Audet, Y., Savaria, Y., Rufenacht, H., Gloutnay, E., Blaquière, Y., Moupfouma, F., & Batani, N. (2012). On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations. IEEE Transactions on Nuclear Science, 59(6), 2959-65. External link

Al-Terkawi Hasib, O., André, W., Blaquière, Y., & Savaria, Y. (2012, May). Propagating analog signals through a fully digital network on an electronic system prototyping platform [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of. External link

2011

Laflamme-Mayer, N., Sawan, M., & Blaquière, Y. (2011, June). A dual-power rail, low-dropout, fast-response linear regulator dedicated to a wafer-scale electronic systems prototyping platform [Paper]. 9th IEEE International New Circuits and Systems Conference (NEWCAS 2011), Bordeaux, France. External link

Diop, M. D., Radji, M., André, W., Blaquière, Y., Hamoui, A. A., & Izquierdo, R. (2010, October). Electrical characterization of annular through silicon vias for a reconfigurable wafer-sized circuit board [Paper]. IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, Austin, TX, United states. External link

Laflamme-Mayer, N., Blaquière, Y., & Sawan, M. (2011, December). A large range and fine tuning configurable Bandgap reference dedicated to wafer-scale systems [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link

Valorge, O., André, W., Savaria, Y., & Blaquière, Y. (2011, June). Power supply analysis of a large area integrated circuit [Paper]. 9th IEEE International New Circuits and Systems Conference (NEWCAS 2011), Bordeaux, France. External link

2008

Norman, R., Valorge, O., Blaquière, Y., Lepercq, É., Basile-Bellavance, Y., El-Alaoui, Y., Prytula, R., & Savaria, Y. (2008, June). An active reconfigurable circuit board [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, QC, Canada. External link

Valorge, O., Nguyen, A. T., Blaquière, Y., Norman, R., & Savaria, Y. (2008, August). Digital signal propagation on a wafer-scale smart active programmable interconnect [Paper]. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), St. Julian's, Malta. External link

Bougataya, M., Lakhsasi, A., Norman, R., Prytula, R., Blaquière, Y., & Savaria, Y. (2008, May). Steady state thermal analysis of a reconfigurable wafer-scale circuit board [Paper]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2008), Niagara Falls, Ont.. External link

1998

Cantin, M.-A., Blaquière, Y., Savaria, Y., Granger, É., & Lavoie, P. (1998, May). Implementation fo the Fuzzy ART neural network for fast clustering of radar pulses [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1998), Monterey, CA, USA. External link

1997

Granger, É., Savaria, Y., Blaquière, Y., Cantin, M.-A., & Lavoie, P. (1997). A VLSI architecture for fast clustering with fuzzy ART neural networks. Journal of Microelectronic Systems Integration, 5(1), 3-18. Unavailable

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