Documents publiés en "1994"

A

Abderrahman, A., Kaminska, B., & Savaria, Y. (février 1994). Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits [Communication écrite]. European Design and Test Conference, Paris, Fr. Lien externe

Amellal, S., & Kaminska, B. (1994). Functional synthesis of digital systems with TASS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(5), 537-552. Lien externe

Aourid, S. M., & Kaminska, B. (juin 1994). Neural networks for the set covering problem: An application to the test vector compaction [Communication écrite]. 1994 IEEE International Conference on Neural Networks, Orlando, FL, USA. Lien externe

Arabi, K., Kaminska, B., & Rzeszut, J. (novembre 1994). Built-in self-test approach for medium to high-resolution digital-to-analog converters [Communication écrite]. 3rd Asian Test Symposium, Nara, Japon. Lien externe

Arabi, K., Kaminska, B., & Rzeszut, J. (novembre 1994). New built-in self-test approach for digital-to-analog and analog-to-digital converters [Communication écrite]. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, USA. Publié dans IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Lien externe

Ayari, B., & Kaminska, B. (1994). New dynamic test vector compaction for automatic test pattern generation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(3), 353-358. Lien externe

B

BenHamida, H., & Kaminska, B. (mai 1994). High level synthesis with testability constraints [Communication écrite]. IEEE International Symposium on Circuits and Systems - ISCAS '94, London, UK. Lien externe

BenHamida, N., Kaminska, B., & Savaria, Y. (mai 1994). Pseudo-random vector compaction for sequential testability [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe

F

Fares, M., & Kaminska, B. (1994). Exploring test space with fuzzy decision making. IEEE Design & Test of Computers, 11(3), 17-27. Lien externe

Fares, M., & Kaminska, B. (1994). Fuzzy optimization models for analog test decisions. Journal of Electronic Testing: Theory and Applications (JETTA), 5(2-3), 299-305. Lien externe

H

Hamida, N. B., & Kaminska, B. (janvier 1994). Multiple fault testing in analog circuits [Communication écrite]. 7th International Conference on VLSI Design, Calcutta, India. Lien externe

J

Jamoussi, M., & Kaminska, B. (janvier 1994). Data path testability evaluation via functional testability measures [Communication écrite]. 7th International Conference on VLSI Design, Calcutta, India. Lien externe

Jamoussi, M., & Kaminska, B. (février 1994). M-testability: An approach for data-path testability evaluation [Communication écrite]. European Design and Test Conference, Paris, Fr. Lien externe

Jamoussi, M., Kaminska, B., & Mukhedkar, D. (1994). Testability of one-dimensional iterative arrays using a variable testability measure. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 41(1), 82-86. Lien externe

L

Lejmi, S., Kaminska, B., & Wagneur, E. (octobre 1994). Retiming for the global optimization of synchronous sequential circuits [Communication écrite]. IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA. Non disponible

M

Mheir-El-Saadi, F., & Kaminska, B. (1994). Automatic hierarchical delay analysis tool. Journal of Computer Science and Technology, 9(4), 349-364. Lien externe

R

Rayapati, V. N., & Kaminska, B. (1994). A dynamic reconfiguration scheme for mega bit static random access memories. Microelectronics and reliability, 34(1), 107-114. Lien externe

Rayapati, V. N., & Kaminska, B. (août 1994). Mega bit BiCMOS SRAM chip package modelling and performance analysis [Communication écrite]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, Cal, USA. Lien externe

Rayapati, V. N., & Kaminska, B. (août 1994). Mega bit CMOS SRAM chip failure analysis using external electrical testing and internal contactless laser beam testing [Communication écrite]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, Cal, USA. Lien externe

S

Slamani, M., & Kaminska, B. (avril 1994). Multifrequency testability analysis for analog circuits [Communication écrite]. 12th IEEE VLSI Test Symposium, Cherry Hill, NJ, USA. Lien externe

Slamani, M., Kaminska, B., & Quesnel, G. (octobre 1994). Integrated approach for analog circuit testing with a minimum number of detected parameters [Communication écrite]. 1994 IEEE International Test Conference, Washington, DC, USA. Lien externe

Sokolowska, E., & Kaminska, B. (octobre 1994). Application of optoelectronic techniques to high speed testing [Communication écrite]. 1994 IEEE International Test Conference, Washington, DC, USA. Lien externe

Soufi, M., Savaria, Y., Kaminska, B., & Darlay, F. (1994). Producing reliable initialization and test of sequential circuits with pseudo-random vectors. (Rapport technique n° EPM-RT-94-23). Accès restreint