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Abubakr, A., Hassan, A., Ragab, A., Yacout, S., Savaria, Y., & Sawan, M. (mai 2018). High-temperature modeling of the I-V characteristics of GaN150 HEMT using machine learning techniques [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italie (5 pages). Lien externe
Amer, M., Hassan, A., Ragab, A., Yacout, S., Savaria, Y., & Sawan, M. (mai 2018). High-Temperature Empirical Modeling for the I-V Characteristics of GaN150-Based HEMT [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy. Lien externe
Ammar, M., Hamad, G. B., Mohamed, O. A., & Savaria, Y. (décembre 2018). Reliability Analysis of the SPARC V8 Architecture via Fault Trees and UPPAL-SMC [Communication écrite]. 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2018), Bordeaux, France. Lien externe
Assaf, H., Savaria, Y., & Sawan, M. (décembre 2018). Vector matrix multiplication using crossbar arrays: a comparative analysis [Communication écrite]. 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2018), Bordeaux, France. Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (mai 2018). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (2018). A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 1939-1952. Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (juin 2018). HPQ: a high capacity hybrid priority queue architecture for high-speed network switches [Communication écrite]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. Lien externe
Berrima, S., Blaquière, Y., & Savaria, Y. (2018). Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integration, 62, 159-169. Lien externe
Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (mai 2018). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models [Communication écrite]. International Conference on Pattern Recognition and Artificial Intelligence (ICPRAI 2018), Montréal, Québec. Non disponible
Fradj, B., Wolff, B., Bélanger, N., & Savaria, Y. (mai 2018). Implementation of a cache-based IPv6 lookup system with hashing [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (4 pages). Lien externe
Gemieux, M., Li, M., Savaria, Y., David, J. P., & Zhu, G. (2018). A Hybrid Architecture with Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access, 6, 62826-62839. Lien externe
Hamad, G. B., Ammar, M., Mohamed, O. A., & Savaria, Y. (2018). New insights into soft-faults induced cardiac pacemakers malfunctions analyzed at system-level via model checking. IEEE Access, 6, 62107-62119. Lien externe
Hamad, G. B., Ammar, M., Mohamed, O. A., & Savaria, Y. (septembre 2018). System-Level Characterization, Modeling, and Probabilistic Formal Analysis of LEON3 Vulnerability to Transient Faults [Communication écrite]. 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2018), Piscataway, NJ, USA (4 pages). Lien externe
Hasib, O. A.-T., Crepeau, D., Awad, T., Dulipovici, A., Savaria, Y., & Thibeault, C. (avril 2018). Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits [Communication écrite]. 36th IEEE VLSI Test Symposium (VTS 2018), Los Alamitos, CA (6 pages). Lien externe
Hassan, A., Savaria, Y., & Sawan, M. (2018). Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 2085-2098. Disponible
Hassan, A., Savaria, Y., & Sawan, M. (2018). GaN Integration Technology, an Ideal Candidate for High-Temperature Applications: A Review. IEEE Access, 6, 78790-78802. Lien externe
Laflamme-Mayer, N., Kowarzyk, G., Blaquiere, Y., Savaria, Y., & Sawan, M. (2018). A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(2), 304-315. Lien externe
Léonardon, M., Leroux, C., Binet, D., Langlois, J. M. P., Jégo, C., & Savaria, Y. (mai 2018). Custom low power processor for polar decoding [Communication écrite]. IEEE International Symposium on Circuits & Systems (ISCAS 2018), Florence, Italy. Lien externe
Leonardon, M., Leroux, C., Jaaskelainen, P., Jego, C., & Savaria, Y. (décembre 2018). Transport Triggered Polar Decoders [Communication écrite]. 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing (ISTC 2018), Hong Kong (5 pages). Lien externe
Lepercq, É., Blaquière, Y., & Savaria, Y. (2018). A pattern-based routing algorithm for a novel electronic system prototyping platform. Integration, 62, 224-237. Lien externe
Li, M., Chen, C., Zhu, G., & Savaria, Y. (août 2018). Local Queueing-Based Data-Driven Task Scheduling for Multicore Systems [Communication écrite]. 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada. Lien externe
Meng, L., Zhu, G., & Savaria, Y. (mai 2018). Delay bound analysis for heterogeneous multicore systems using network calculus [Communication écrite]. 13th IEEE Conference on Industrial Electronics and Applications (ICIEA 2018), Wuhan, China. Lien externe
Mohajertehrani, M., Savaria, Y., & Sawan, M. (2018). Harvesting energy from aviation data lines: implementation and experimental results. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(6), 2048-2057. Lien externe
Noghabaei, S. M., Radin, R. L., Savaria, Y., & Sawan, M. (mai 2018). A High-Efficiency Ultra-Low-Power CMOS Rectifier for RF Energy Harvesting Applications [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (4 pages). Lien externe
Pal, N., Kilaru, A., Savaria, Y., & Lakhssassi, A. (juin 2017). Hybrid features of tamura texture and shape-based image retrieval [Communication écrite]. 5th International Conference on Advanced Computing, Networking, and Informatics (ICACNI 2017), Goa, India. Lien externe
Pal, N., Kilaru, A., Savaria, Y., & Lakhssassi, A. (juillet 2018). Thermal image processing to Recognize and Quantify Pain in Human Body [Communication écrite]. International Conference on Smart Computing and Electronic Enterprise (ICSCEE 2018), Shah Alam, Malaysia (5 pages). Lien externe
Stimpfling, T., Langlois, J. M. P., Bélanger, N., & Savaria, Y. (mai 2018). A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis [Communication écrite]. 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018), Washington, D.C.. Lien externe
Trigui, A., Ali, M., Ammari, A. C., Savaria, Y., & Sawan, M. (2018). A 1.5-pJ/bit, 9.04-Mbit/s Carrier-Width Demodulator for Data Transmission Over an Inductive Link Supporting Power and Data Transfer. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(10), 1420-1424. Lien externe
Vakili, S., Langlois, J. M. P., Savaria, Y., & Manjikian, N. (2018). Enhanced Bloom filter utilisation scheme for string matching using a splitting approach. IET Communications, 12(7), 868-875. Lien externe
Wolff, B., Fradj, B., Belanger, N., & Savaria, Y. (août 2018). Extending a CPU Cache for Efficient IPv6 Lookup [Communication écrite]. 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada. Lien externe
