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Audet, D., & Savaria, Y. (1994). Architectural approach for increasing clock frequency and communication speed in monolithic WSI systems. IEEE Transactions on Components Packaging and Manufacturing Technology. Part B, Advanced Packaging, 17(3), 362-368. Lien externe
Audet, D., Savaria, Y., & Arel, N. (1994). Pipelining communications in large VLSI/ULSI systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(1), 1-10. Lien externe
Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M. A., & Morawski, R. Z. (1994). An integrated structure for kalman-filter-based measurand reconstruction. IEEE Transactions on Instrumentation and Measurement, 43(3), 403-410. Lien externe
Bélanger, N., Haccoun, D., & Savaria, Y. (1994). A multiprocessor architecture for multiple path stack sequential decoders. IEEE Transactions on Communications, 42(2-4, pt.2), 951-957. Lien externe
Lavoie, P., Haccoun, D., & Savaria, Y. (1994). Systolic architecture for fast stack sequential decoders. IEEE Transactions on Communications, 42(2/3/4, pt.), 324-335. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1994). A fast method to evaluate the optimum number of spares in defect-tolerant integrated-circuits. IEEE Transactions on Computers, 43(6), 687-697. Lien externe
Nekili, M., Bois, G., & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid h-trees. (Rapport technique n° EPM-RT-94-09). Accès restreint
Soufi, M., Savaria, Y., Kaminska, B., & Darlay, F. (1994). Producing reliable initialization and test of sequential circuits with pseudo-random vectors. (Rapport technique n° EPM-RT-94-23). Accès restreint
Abderrahman, A., Kaminska, B., & Savaria, Y. (février 1994). Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits [Communication écrite]. European Design and Test Conference, Paris, Fr. Lien externe
Audet, D., Savaria, Y., & Arel, N. (janvier 1994). Architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems [Communication écrite]. 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, California. Lien externe
Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M.-A., & Morawski, R. Z. (mai 1994). An application-specific processor dedicated to Kalman-filter-based correction of spectrometric data [Communication écrite]. IEEE Instrumentation and Measurement Technology Conference (IMTC 1994), Hamamatsu, Japan. Lien externe
BenHamida, N., Kaminska, B., & Savaria, Y. (mai 1994). Pseudo-random vector compaction for sequential testability [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe
Crespo, J.-F., Lavoie, P., & Savaria, Y. (mai 1994). Fast convergence with low precision weights in ART1 networks [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe
Ghannoum, S., Chtchvyrkov, D., & Savaria, Y. (mai 1994). Comparative study of single-phase clocked latches using estimation criteria [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe
Ghannoum, S., Chtchvyrkov, D., & Savaria, Y. (août 1994). Single-clock dynamic latches optimization [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
Kermouche, R., & Savaria, Y. (octobre 1994). Defect and fault tolerant scan chains [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1994), Montréal, Québec. Lien externe
Kermouche, R., Savaria, Y., & Audet, D. (janvier 1994). Harvest model of an integrated hierarchical-bus architecture [Communication écrite]. 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, CA, USA. Lien externe
Kroumba, S. M., Bois, G., & Savaria, Y. (août 1994). Synthesis approach for the generation of parallel architectures [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
Nekili, M., Savaria, Y., & Bois, G. (mai 1994). Fast low-power driver for long interconnections in VLSI systems [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, UK. Lien externe
Nekili, M., Savaria, Y., & Bois, G. (août 1994). A variable-size parallel regenerator for long integrated interconnections [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
Savaria, Y., Chtchvyrkov, D., & Currie, J. F. (mai 1994). Fast CMOS voltage-controlled ring oscillator [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe
St-Amand, R., Savaria, Y., & Sawan, M. (août 1994). Design optimization of a current source for microstimulator applications [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
St.-Amand, R., Sawan, M., & Savaria, Y. (novembre 1994). Generation of balanced bipolar stimuli based on current sources without coupling capacitor [Communication écrite]. 16th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 1994), Baltimore, MD, USA. Lien externe
Savaria, Y. (1994). Parallel microprocessor architecture. (Brevet no US5276893). Lien externe
