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Ayachi, D., Savaria, Y., & Thibeault, C. (juin 2009). A configurable platform for MPSoCs based on application specific instruction set processors [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
Bouanen, S., Thibeault, C., Savaria, Y., & Tremblay, J. P. (octobre 2013). Fault tolerant smart transducer interface for safety-critical avionics applications [Communication écrite]. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA. Lien externe
Boland, J. F., Chureau, A., Thibeault, C., Savaria, Y., Gagnon, F., & Zilic, Z. (juin 2004). An efficient methodology for design and verification of an equalizer for a software defined radio [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Chureau, A., Savaria, Y., Boland, J.-F., Zilic, Z., Thibeault, C., & Gagnon, F. (juin 2006). Building heterogeneous functional prototypes using articulated interfaces [Communication écrite]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Lien externe
Crepeau, J., Thibeault, C., & Savaria, Y. (octobre 1993). Some results on yield and local design rule relaxation [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1993), Venice, Italy. Lien externe
Fiorentino, M., Savaria, Y., & Thibeault, C. (juin 2017). FPGA implementation of Token-based Self-timed processors: A case study [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
Fiorentino, M., Savaria, Y., Thibeault, C., & Gervais, P. (mai 2016). A practical design method for prototyping self-timed processors using FPGAs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. Lien externe
Gagnon, Y., Meunier, M., Savaria, Y., & Thibeault, C. (octobre 1997). Mathematical cost model for redundant multi-processor arrays [Communication écrite]. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France. Publié dans Journal of Microelectronic Systems Integration, 5(4). Non disponible
Hobeika, C., Pichette, S., Leonard, M. A., Thibeault, C., Boland, J. F., & Audet, Y. (juillet 2014). Multi-abstraction level signature generation and comparison based on radiation single event upset [Communication écrite]. 20th IEEE International On-Line Testing Symposium (IOLTS 2014), Catalunya, Spain. Lien externe
Kafrounni, M., Thibeault, C., & Savaria, Y. (janvier 1997). Cost model for VLSI/MCM systems [Communication écrite]. IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France. Lien externe
Monte, G., Antaki, B., Patenaude, S., Savaria, Y., Thibeault, C., & Trouborst, P. (avril 2001). Tools for the characterization of bipolar CML testability [Communication écrite]. 19th IEEE VLSI Test Symposium (VTS 2001), Marina Del Rey, CA, USA. Lien externe
Robache, R., Boland, J.-F., Thibeault, C., & Savaria, Y. (juin 2013). A methodology for system-level fault injection based on gate-level faulty behavior [Communication écrite]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. Lien externe
Sahraii, N., Savaria, Y., Thibeault, C., & Gagnon, F. (juin 2008). Scheduling of turbo decoding on a multiprocessor platform to manage its processing effort variability [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Savaria, Y., Thibeault, C., & Ivanov, A. (1996). IEEE VSLI test symposium - meeting the quality challenge. IEEE Design & Test of Computers, 13(3), 110-112. Non disponible
Tazi, F. Z., Thibeault, C., & Savaria, Y. (mai 2016). Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA [Communication écrite]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2016), Vancouver, British Columbia (5 pages). Lien externe
Thibeault, C., Hariri, Y., Hasan, S. R., Hobeika, C., Savaria, Y., Audet, Y., & Tazi, F. Z. (2013). A library-based early soft error sensitivity analysis technique for SRAM-based FPGA design. Journal of Electronic Testing: Theory and Applications, 29(4), 457-471. Lien externe
Thibeault, C., Pichette, S., Audet, Y., Savaria, Y., Rufenacht, H., Gloutnay, E., Blaquiere, Y., Moupfouma, F., & Batani, N. (2012). On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations. IEEE Transactions on Nuclear Science, 59(6), 2959-65. Lien externe
Tremblay, J.-P., Savaria, Y., Thibeault, C., & Mbaye, M. (octobre 2008). Improving resource utilization in an multiple asynchronous ALU DSP architecture [Communication écrite]. 1st Microsystems and Nanoelectronics Research Conference. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1995). Equivalence proofs of some yield modeling methods for defect-tolerant integrated-circuits. IEEE Transactions on Computers, 44(5), 724-728. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1994). A fast method to evaluate the optimum number of spares in defect-tolerant integrated-circuits. IEEE Transactions on Computers, 43(6), 687-697. Lien externe
Thibeault, C., & Savaria, Y. (novembre 1992). Comparing results from defect-tolerant yield models [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1992), Dallas, TX, United states. Lien externe