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Savaria, Y., Thibeault, C., & Ivanov, A. (1996). IEEE VSLI test symposium - meeting the quality challenge. IEEE Design & Test of Computers, 13(3), 110-112. Non disponible
Thibeault, C., Savaria, Y., & Houle, J.-L. (1995). Equivalence proofs of some yield modeling methods for defect-tolerant integrated-circuits. IEEE Transactions on Computers, 44(5), 724-728. Lien externe
Hobeika, C., Pichette, S., Leonard, M. A., Thibeault, C., Boland, J. F., & Audet, Y. (juillet 2014). Multi-abstraction level signature generation and comparison based on radiation single event upset [Communication écrite]. 20th IEEE International On-Line Testing Symposium (IOLTS 2014), Catalunya, Spain. Lien externe
Robache, R., Boland, J.-F., Thibeault, C., & Savaria, Y. (juin 2013). A methodology for system-level fault injection based on gate-level faulty behavior [Communication écrite]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. Lien externe
Ayachi, D., Savaria, Y., & Thibeault, C. (juin 2009). A configurable platform for MPSoCs based on application specific instruction set processors [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France (4 pages). Lien externe
Boland, J. F., Chureau, A., Thibeault, C., Savaria, Y., Gagnon, F., & Zilic, Z. (juin 2004). An efficient methodology for design and verification of an equalizer for a software defined radio [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Kafrounni, M., Thibeault, C., & Savaria, Y. (octobre 1997). Cost model for VLSI/MCM systems [Communication écrite]. IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France. Lien externe
Gagnon, Y., Meunier, M., Savaria, Y., & Thibeault, C. (octobre 1997). Mathematical cost model for redundant multi-processor arrays [Communication écrite]. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France. Publié dans Journal of Microelectronic Systems Integration, 5(4). Non disponible
Crépeau, J., Thibeault, C., & Savaria, Y. (octobre 1993). Some results on yield and local design rule relaxation [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1993), Venice, Italy. Lien externe
Thibeault, C., & Savaria, Y. (novembre 1992). Comparing results from defect-tolerant yield models [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1992), Dallas, TX, United states. Lien externe
