Documents dont l'auteur est "Gagnon, Yves"

2011

Singh, R., Audet, Y., Gagnon, Y., Savaria, Y., Boulais, E., & Meunier, M. (2011). A laser-trimmed rail-to-rail precision CMOS operational amplifier. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(2), 75-79. Lien externe

2009

Lacourse, A., Ducharme, M., St-Jean, H., Gagnon, Y., Savaria, Y., & Meunier, M. (2009). Tunable semiconductor component provided with a current barrier. (Brevet no US7564078). Lien externe

2007

Singh, R., Audet, Y., Gagnon, Y., & Savaria, Y. (mai 2007). Integrated circuit trimming technique for offset reduction in a precision CMOS amplifier [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, USA. Lien externe

Binet, V., Savaria, Y., Meunier, M., & Gagnon, Y. (mai 2007). Modeling the substrate noise injected by a DC-DC converter [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), Phoenix-Scottsdale, AZ. Lien externe

2003

Turcotte, D., Ouellette, C., Gagnon, Y., Posada, É., Bourgault, M., & Nollet, J. (2003). Ministère de la Santé et des Services sociaux du Québec : Acquisition d'un système de télécommunications. Revue internationale de cas en gestion, 1(1), 1-7. Lien externe

2001

Gagnon, Y., Meunier, M., & Savaria, Y. (2001). Method and apparatus for iteratively, selectively tuning the impedance of integrated semiconductor devices using a focussed heating source. (Brevet no US6329272). Lien externe

1997

Gagnon, Y., Savaria, Y., Meunier, M., & Thibeault, C. (octobre 1997). Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1997), Paris, Fr. Lien externe