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Word cloudA word cloud is a visual representation of the most frequently used words in a text or a set of texts. The words appear in different sizes, with the size of each word being proportional to its frequency of occurrence in the text. The more frequently a word is used, the larger it appears in the word cloud. This technique allows for a quick visualization of the most important themes and concepts in a text.
In the context of this page, the word cloud was generated from the publications of the author {}. The words in this cloud come from the titles, abstracts, and keywords of the author's articles and research papers. By analyzing this word cloud, you can get an overview of the most recurring and significant topics and research areas in the author's work.
The word cloud is a useful tool for identifying trends and main themes in a corpus of texts, thus facilitating the understanding and analysis of content in a visual and intuitive way.
Berrima, S. (2021). Convertisseurs temps-numérique distribués et à mesures multiples pour FPGA [Ph.D. thesis, Polytechnique Montréal]. Available
Berrima, S., Blaquière, Y., & Savaria, Y. (2021). Ring-Oscillator Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. IEEE Transactions on Instrumentation and Measurement, 70, 1-10. External link
Berrima, S., Blaquière, Y., & Savaria, Y. (2020). Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. IET Circuits Devices & Systems, 14(8), 1243-1252. External link
Berrima, S., Blaquière, Y., & Savaria, Y. (2018). Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integration, 62, 159-169. External link
Berrima, S., Blaquière, Y., & Savaria, Y. (2017, May). A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD (4 pages). External link
Berrima, S., Blaquière, Y., & Savaria, Y. (2017, August). Sub-ps resolution programmable delays implemented in a Xilinx FPGA [Paper]. 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Boston, MA. External link
Berrima, S. (2014). Algorithmes de diagnostic d'une chaîne JTAG reconfigurable et tolérante aux pannes au sein de la technologie WaferIC [Master's thesis, École Polytechnique de Montréal]. Available
Blaquière, Y., Basile-Bellavance, Y., Berrima, S., & Savaria, Y. (2014, June). Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, VIC, Australia (4 pages). External link
