Documents publiés en "1995"

A

Audet, D., & Savaria, Y. (1995). Effective ultra large scale integration (ULSI) architecture techniques : the host interface. (Rapport technique). Non disponible

Audet, D., & Savaria, Y. (1995). Effective ultra large scale integration (ULSI) architecture techniques : the routers, from a functional to a detailed implementation description. (Rapport technique). Non disponible

Audet, D., & Savaria, Y. (1995). High-speed interconnections using true single-phase clocking. Journal of Microelectronic Systems Integration, 3(4), 247-257. Non disponible

Audet, D., & Savaria, Y. High-speed interconnections using true single-phase clocking [Communication écrite]. 7th IEEE Annual International Conference on Wafer Scale Integration, San Francisco, Ca, USA. Lien externe

Audet, D., Savaria, Y., & Arel, N. (1995). Effective ultra large scale integration (ULSI) architecture techniques: FATMOS, a fault-tolerant multiprocessor operating system. (Rapport technique). Non disponible

B

Barwicz, A., Massicotte, D., Savaria, Y., Pango, P. A., & Morawski, R. Z. (1995). An application-specific processor dedicated to kalman-filter-based correction of spectrometric data. IEEE Transactions on Instrumentation and Measurement, 44(3), 720-724. Lien externe

Belzile, J., Savaria, Y., Haccoun, D., & Chalifoux, M. (1995). Bounds on the performance of partial selection networks. IEEE Transactions on Communications, 43(2-4), 1800-1809. Lien externe

Blaquiere, T., Gagné, G., Savaria, Y., & Évéquoz, C. (1995). A new efficient algorithmic-based seu tolerant system architecture. IEEE Transactions on Nuclear Science, 42(6), 1599-1606. Lien externe

G

Gadiri, A., Savaria, Y., & Kaminska, B. (septembre 1995). Optimized CMOS compatible photoreceiver [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montréal, QC, Canada. Lien externe

K

Kermouche, R., Audet, D., & Savaria, Y. (1995). On the optimization of integrated hierarchical bus architectures to achieve efficient fault-tolerance. Journal of Microelectronic Systems Integration, 3(1), 47-63. Non disponible

Khali, H., Savaria, Y., Houle, J.-L., Beraldin, J. A., Blais, F., & Rioux, M. (septembre 1995). VLSI chip for 3-D camera calibration [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montréal, Québec. Lien externe

R

Rzeszut, J., Kaminska, B., & Savaria, Y. (novembre 1995). New method for testing mixed analog and digital circuits [Communication écrite]. 4th Asian Test Symposium, Bangalore, India. Lien externe

S

Sawan, M., St-Amand, R., & Savaria, Y. (décembre 1995). Design and optimization of programmable biphasic current-sources [Communication écrite]. 2nd annual International Conference on Electronics, Circuits and Systems (ICECS 1995), Amman, Jordan. Non disponible

Soufi, M., Savaria, Y., & Kaminska, B. (avril 1995). On the design of at-speed testable VLSI circuits [Communication écrite]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. Lien externe

Soufi, M., Savaria, Y., & Kaminska, B. (avril 1995). On Using partial reset for pseudo-random testing [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1995), Seattle, WA, USA. Lien externe

Soufi, M., Savaria, Y., Darlay, F., & Kaminska, B. (1995). Producing reliable initialization and test of sequential circuits with pseudorandom vectors. IEEE Transactions on Computers, 44(10), 1251-1256. Lien externe

T

Thibeault, C., Savaria, Y., & Houle, J.-L. (1995). Equivalence proofs of some yield modeling methods for defect-tolerant integrated-circuits. IEEE Transactions on Computers, 44(5), 724-728. Lien externe