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Awwad, F. R., Nekili, M., & Sawan, M. (2012). A Novel Theory on Parallel Repeater-Insertion Methodologies for Long on-Chip Interconnects. International Journal of Circuit Theory and Applications, 40(7), 693-708. Lien externe
Awwad, F. R., Nekili, M., Ramachandran, V., & Sawan, M. (2008). On modeling of parallel repeater-insertion methodologies for SoC interconnects. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(1), 322-335. Lien externe
Nekili, M., Bois, G., & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174. Lien externe
Nekili, M., Bois, G., & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid h-trees. (Rapport technique n° EPM-RT-94-09). Accès restreint
Awwad, F. R., Nekili, M., & Sawan, M. (juin 2008). Performance metrics study for repeater-insertion strategies [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec. Lien externe
Nekili, M., & Savaria, Y. (mai 1992). Optimal methods of driving interconnections in VLSI circuits [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. Lien externe
Nekili, M. (1998). Synthèse de réseaux de distribution d'horloges en présence de variations du procédé de fabrication [Thèse de doctorat, École Polytechnique de Montréal]. Disponible