 | Up a level |
Awwad, F. R., Nekili, M., & Sawan, M. (2012). A Novel Theory on Parallel Repeater-Insertion Methodologies for Long on-Chip Interconnects. International Journal of Circuit Theory and Applications, 40(7), 693-708. External link
Awwad, F. R., Nekili, M., Ramachandran, V., & Sawan, M. (2008). On modeling of parallel repeater-insertion methodologies for SoC interconnects. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(1), 322-335. External link
Awwad, F. R., Nekili, M., & Sawan, M. (2008, June). Performance metrics study for repeater-insertion strategies [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec. External link
Hasan, S. K., Landry, A., Savaria, Y., & Nekili, M. (2004, June). Design constraints of hypertransport-compatible networks-on-chip [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, QC, Canada. External link
Landry, A., Savaria, Y., & Nekili, M. (2005, June). Circuits techniques for a 2 GHz AMBA AHB Bus [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, QC, Canada. External link
Landry, A., Nekili, M., & Savaria, Y. (2005, May). A novel 2 GHz Mulit-layer AMBA high-Speed bus interconnect matrix for SoC platforms [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. External link
Landry, A., Savaria, Y., & Nekili, M. (2004, December). A beyond-1 GHz high-speed bus for SoC DSP platforms [Paper]. 16th International Conference on Microelectronics (ICM 2004), Tunis, Tunisia. External link
Nekili, M., Savaria, Y., & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84. External link
Nekili, M., Savaria, Y., Bois, G., Bayoumi, M. A., & Jullien, G. (1998, February). Design of clock distribution networks in presence of process variations [Paper]. 8th Great Lakes Symposium on VLSI, Lafayette, LA, USA. External link
Nekili, M. (1998). Synthèse de réseaux de distribution d'horloges en présence de variations du procédé de fabrication [Ph.D. thesis, École Polytechnique de Montréal]. Available
Nekili, M., Bois, G., & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174. External link
Nekili, M., Bois, G., & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid h-trees. (Technical Report n° EPM-RT-94-09). Restricted access
Nekili, M., Savaria, Y., & Bois, G. (1994, May). Fast low-power driver for long interconnections in VLSI systems [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, UK. External link
Nekili, M., Savaria, Y., & Bois, G. (1994, August). A variable-size parallel regenerator for long integrated interconnections [Paper]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. External link
Nekili, M., & Savaria, Y. (1992, May). Optimal methods of driving interconnections in VLSI circuits [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. External link
