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Awwad, F. R., Nekili, M., & Sawan, M. (2012). A Novel Theory on Parallel Repeater-Insertion Methodologies for Long on-Chip Interconnects. International Journal of Circuit Theory and Applications, 40(7), 693-708. Lien externe
Awwad, F. R., Nekili, M., Ramachandran, V., & Sawan, M. (2008). On modeling of parallel repeater-insertion methodologies for SoC interconnects. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(1), 322-335. Lien externe
Awwad, F. R., Nekili, M., & Sawan, M. (juin 2008). Performance metrics study for repeater-insertion strategies [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec. Lien externe
Landry, A., Savaria, Y., & Nekili, M. (juin 2005). Circuits techniques for a 2 GHz AMBA AHB Bus [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, QC, Canada. Lien externe
Landry, A., Nekili, M., & Savaria, Y. (mai 2005). A novel 2 GHz Mulit-layer AMBA high-Speed bus interconnect matrix for SoC platforms [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Landry, A., Savaria, Y., & Nekili, M. (décembre 2004). A beyond-1 GHz high-speed bus for SoC DSP platforms [Communication écrite]. 16th International Conference on Microelectronics (ICM 2004), Tunis, Tunisia. Lien externe
Hasan, S. K., Landry, A., Savaria, Y., & Nekili, M. (juin 2004). Design constraints of hypertransport-compatible networks-on-chip [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, QC, Canada. Lien externe
Nekili, M., Savaria, Y., & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84. Lien externe
Nekili, M., Savaria, Y., Bois, G., Bayoumi, M. A., & Jullien, G. (février 1998). Design of clock distribution networks in presence of process variations [Communication écrite]. 8th Great Lakes Symposium on VLSI, Lafayette, LA, USA. Lien externe
Nekili, M. (1998). Synthèse de réseaux de distribution d'horloges en présence de variations du procédé de fabrication [Thèse de doctorat, École Polytechnique de Montréal]. Disponible
Nekili, M., Bois, G., & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174. Lien externe
Nekili, M., Bois, G., & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid h-trees. (Rapport technique n° EPM-RT-94-09). Accès restreint
Nekili, M., Savaria, Y., & Bois, G. (mai 1994). Fast low-power driver for long interconnections in VLSI systems [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, UK. Lien externe
Nekili, M., Savaria, Y., & Bois, G. (août 1994). A variable-size parallel regenerator for long integrated interconnections [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
Nekili, M., & Savaria, Y. (mai 1992). Optimal methods of driving interconnections in VLSI circuits [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. Lien externe
