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Bettayeb, B., Bassetto, S., Vialletelle, P., & Tollenaere, M. (2012). Quality and exposure control in semiconductor manufacturing. Part I: Modelling. International Journal of Production Research, 50(23), 6835-6851. Lien externe
Bettayeb, B., Bassetto, S., Vialletelle, P., & Tollenaere, M. (2012). Quality and exposure control in semiconductor manufacturing. Part II: Evaluation. International Journal of Production Research, 50(23), 6852-6869. Lien externe
Bettayeb, B., Tollenaere, M., & Bassetto, S. (octobre 2011). Plan de surveillance basé sur l'exposition aux risques et les capabilités des ressources [Communication écrite]. 9e Congrès international de génie industriel (CIGI 2011), Saint-Sauveur, Québec. Non disponible
Bettayeb, B., Vialletelle, P., Bassetto, S., & Tollenaere, M. (novembre 2010). Operational risk evaluation and control plan design [Communication écrite]. 13th ARCSIS Technical & Scientific Meeting, Manufacturing Challenges in European Semiconductor Fabs, Rousset, France. Non disponible
Bettayeb, B., Vialletelle, P., Bassetto, S., & Tollenaere, M. (octobre 2010). Optimized design of control plans based on risk exposure and ressources capabilites [Communication écrite]. International Symposium on Semiconductor Manufacturing (ISSM 2010), Tokyo. Japan. Lien externe
Sahnoun, M. , Bettayeb, B., Bassetto, S., & Tollenaere, M. (2014). Simulation-based optimization of sampling plans to reduce inspections while mastering the risk exposure in semiconductor manufacturing. Journal of Intelligent Manufacturing, 27(6), 1335-1349. Lien externe
Sahnoun, M. , Bettayeb, B., Tollenaere, M., & Bassetto, S. (mars 2012). Smart sampling for risk reduction and delay optimisation [Communication écrite]. IEEE International Systems Conference, Vancouver, BC, Canada. Lien externe
