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Bettayeb, B., Bassetto, S., Vialletelle, P., & Tollenaere, M. (2012). Quality and exposure control in semiconductor manufacturing. Part I: Modelling. International Journal of Production Research, 50(23), 6835-6851. External link
Bettayeb, B., Bassetto, S., Vialletelle, P., & Tollenaere, M. (2012). Quality and exposure control in semiconductor manufacturing. Part II: Evaluation. International Journal of Production Research, 50(23), 6852-6869. External link
Bettayeb, B., Tollenaere, M., & Bassetto, S. (2011, October). Plan de surveillance basé sur l'exposition aux risques et les capabilités des ressources [Paper]. 9e Congrès international de génie industriel (CIGI 2011), Saint-Sauveur, Québec. Unavailable
Bettayeb, B., Vialletelle, P., Bassetto, S., & Tollenaere, M. (2010, November). Operational risk evaluation and control plan design [Paper]. 13th ARCSIS Technical & Scientific Meeting, Manufacturing Challenges in European Semiconductor Fabs, Rousset, France. Unavailable
Bettayeb, B., Vialletelle, P., Bassetto, S., & Tollenaere, M. (2010, October). Optimized design of control plans based on risk exposure and ressources capabilites [Paper]. International Symposium on Semiconductor Manufacturing (ISSM 2010), Tokyo. Japan. External link
Sahnoun, M. , Bettayeb, B., Bassetto, S., & Tollenaere, M. (2014). Simulation-based optimization of sampling plans to reduce inspections while mastering the risk exposure in semiconductor manufacturing. Journal of Intelligent Manufacturing, 27(6), 1335-1349. External link
Sahnoun, M. , Bettayeb, B., Tollenaere, M., & Bassetto, S. (2012, March). Smart sampling for risk reduction and delay optimisation [Paper]. IEEE International Systems Conference, Vancouver, BC, Canada. External link
