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Items where Author is "Abderrahman, A."

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Jump to: 2007 | 1999 | 1997 | 1996 | 1994
Number of items: 7.

2007

Abderrahman, A., Savaria, Y., Khouas, A., & Sawan, M. (2007, August). Accurate testability analysis based-on multi-frequency test generation and a new testability metric [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. External link

Abderrahman, A., Savaria, Y., Khouas, A., & Sawan, M. (2007, December). New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches [Paper]. 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco. External link

1999

Abderrahman, A., Cerny, E., & Kamińska, B. (1999). Worst Case Tolerance Analysis and Clp-Based Multifrequency Test Generation for Analog Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(3), 332-345. External link

1997

Abderrahman, A., Cerny, E., & Kamińska, B. (1997, April). CLP-based multifrequency test generation for analog circuits [Paper]. 1997 15th VLSI Test Symposium, Monterey, CA, USA. External link

1996

Abderrahman, A., Savaria, Y., & Kamińska, B. (1996). Analyse, estimation et réduction du bruit de commutation simultanée. [Analysis, estimation and reduction of simultaneous switching noise]. Canadian Journal of Electrical and Computer Engineering, 21(4), 133-143. External link

Abderrahman, A., Cerny, E., & Kamińska, B. (1996). Optimization-based multifrequency test generation for analog circuits. Journal of Electronic Testing: Theory and Applications (JETTA), 9(1-2), 59-73. External link

1994

Abderrahman, A., Kamińska, B., & Savaria, Y. (1994, February). Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits [Paper]. European Design and Test Conference, Paris, Fr. External link

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