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Beaudin, S., Marceau, R. J., Bois, G., Savaria, Y., & Kandil, N. (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), 105-112. Lien externe
Bissou, J. P., & Savaria, Y. (janvier 2003). Conception de haut niveau d'une plate-forme SOC pour la conversion de protocoles réseaux [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). Lien externe
Bissou, J. P., Dubois, M., Savaria, Y., & Bois, G. (décembre 2003). High-speed system bus for a SoC network processing platform [Communication écrite]. 15th International Conference on Microelectronics (ICM 2003), Cairo, Egypt. Lien externe
Boudjella, A., Jin, Z.-F., & Savaria, Y. (octobre 2003). Electrical field analysis of nanoscaled field effect transistors [Communication écrite]. International Microprocesses and Nanotechnology Conference, Tokyo, Japan. Lien externe
Bougataya, M., Lakhsasi, A., Savaria, Y., & Massicotte, D. (janvier 2003). Stress and distortion behavior for VLSI steady state thermal analysis [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). Lien externe
Catudal, S., Cantin, M. A., & Savaria, Y. (2003). Performance driven validation applied to viseo processing. WSEAS Transactions on Electronics, 1(3), 568-574. Non disponible
Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (2003). Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(3), 346-351. Lien externe
Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (avril 2003). Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs [Communication écrite]. Great Lakes Symposium on VLSI (GLSVLSI 2003), Washington, D. C., USA. Lien externe
Ghattas, H., & Savaria, Y. (janvier 2003). Design of dedicated low complexity embedded processors for SOC network processing applications [Communication écrite]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Non disponible
Ghattas, H., Mbaye, M. M., Pepga, J. B., & Savaria, Y. (novembre 2003). SoC platform architecture for a network processor [Communication écrite]. International Symposium on System-on-Chip, Tampere, Finland. Lien externe
Granger, E., Catudal, S., Grou, R., Mbaye, M. M., & Savaria, Y. (2003). On current strategies for hardware acceleration of digital image restoration filters. WSEAS Transactions on Electronics, 1(3), 551-557. Non disponible
Granger, E., Savaria, Y., & Lavoie, P. (2003). A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning. IEEE Transactions on Pattern Analysis and Machine Intelligence, 25(4), 524-528. Lien externe
Jin, Z.-F., Laurin, J.-J., & Savaria, Y. Comparison of Propagation Characteristics Between Single and Coupled Mis Interconnect Topologies in Vlsi Circuits [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). Lien externe
Khali, H., & Savaria, Y. (décembre 2003). Hardware-software co design model for real-time 3D image computation using active laser range finders : a case study [Communication écrite]. 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2003), Sharjah, United Arab Emirates. Lien externe
Khali, H., Savaria, Y., Houle, J. L., Rioux, M., Beraldin, J. A., & Poussart, D. (2003). Improvement of Sensor Accuracy in the Case of a Variable Surface Reflectance Gradient for Active Laser Range Finders. IEEE Transactions on Instrumentation and Measurement, 52(6), 1799-1808. Lien externe
Lamarche, P. H., & Savaria, Y. (janvier 2003). VHDL source code generator and analysis tool to design linear interpolars [Communication écrite]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Non disponible
Lemire, J. F., Aboulhamid, E. M., Savaria, Y., Bois, G., & Baron, A. (janvier 2003). Implementing e assertion checkers from an SDL executable specifications [Communication écrite]. DVCON, San José, USA. Non disponible
Loiseau, L., & Savaria, Y. (2003). Design reuse. Dans System-on-chip for real-time applications (Vol. 711, 29-82). Lien externe
Loiseau, L., & Savaria, Y. (juillet 2002). Methodologies and Strategies for Effective Design-Reuse [Communication écrite]. System-on-Chip for Real-Time Applications. Lien externe
Lu, M., Savaria, Y., Qiu, B., & Taillefer, J. (novembre 2003). IEEE 1149.1 based defect and fault tolerant scan chain for wafer scale integration [Communication écrite]. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, United states. Lien externe
Lu, M., Savaria, Y., Qiu, B., & Taillefer, J. (novembre 2003). IEEE 1149.1 based defect and fault tolerant scan chain for water safe integration [Communication écrite]. 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, MA, USA. Lien externe
Mbaye, M. M., Tohio, B., Savaria, Y., & Pierre, S. Performance of a Firewire-Ethernet Protocols Conversion on an Arm7 Embedded Processor [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). Lien externe
Nicolescu, B., Perronnard, P., Velazco, R., & Savaria, Y. (novembre 2003). Efficiency of transient bit-flips detection by software means a complete study [Communication écrite]. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Cambridge, MA, USA. Lien externe
Nicolescu, B., Savaria, Y., & Velazco, R. (novembre 2003). SIED: software implemented error detection [Communication écrite]. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, United states. Lien externe
Nsame, P., & Savaria, Y. (janvier 2003). System-level design closure [Communication écrite]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Non disponible
Regimbal, S., Lemire, J. F., Savaria, Y., Bois, G., Aboulhamid, M., & Baron, A. (juillet 2002). Aspect Partitioning for Hardware Verification Reuse [Communication écrite]. System-on-Chip for Real-Time Applications. Lien externe
Regimbal, S., Lemire, J.-F., Savaria, Y., Bois, G., Aboulhamid, E. M., & Baron, A. (juin 2003). Automating functional coverage analysis based on an executable specification [Communication écrite]. 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications. Lien externe
Renaud, M., & Savaria, Y. (mai 2003). A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2003). Lien externe
Richard, J. F., Lessard, B., Meingan, R., Martel, S., & Savaria, Y. (janvier 2003). High voltage interfaces for CMOS/DMOS technologies [Communication écrite]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Non disponible
Tang, Y., Qian, L., Wang, Y., & Savaria, Y. (janvier 2003). New memory reference reduction method for FFT implementation on DSP [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand. Lien externe
Tohio, B., Pierre, S., Savaria, Y., & Mbaye, M. M. (mai 2003). Protocol Convertibility in a Network Processing Environment [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003), Montréal, Québec. Lien externe
Trabelsi, A., Savaria, Y., & Audet, Y. (janvier 2003). Automatic offset correction technique based on active load tuning [Communication écrite]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Non disponible
