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Ben Hamida, N., & Kamińska, B. (1993). Multiple fault analog circuit testing by sensitivity analysis. Analog Integrated Circuits and Signal Processing, 4(3), 231-243. Lien externe
Amellal, S., & Kamińska, B. (février 1993). Scheduling algorithm in data path synthesis using the Tabu search technique [Communication écrite]. European Conference on Design Automation (EDAC 1993), Paris, France. Lien externe
BenHamida, N., & Kamińska, B. (octobre 1993). Analog circuit testing based on sensitivity computation and new circuit modeling [Communication écrite]. International Test Conference 1993, Baltimore, MD, USA. Lien externe
Dahmani, A., Savaria, Y., & Kamińska, B. (février 1993). ML-Germinal: A new heuristic standard cell placement algorithm [Communication écrite]. European Conference on Design Automation (EDAC 1993), Paris, France. Lien externe
Fares, M., & Kamińska, B. (avril 1993). A fuzzy decision-making approach for test space exploration [Communication écrite]. 3rd European Test Conference, Rotterdam, Netherlands. Lien externe
Jamoussi, M., & Kamińska, B. (avril 1993). Controllability and observability measures for functional-level testability evaluation [Communication écrite]. 11th IEEE VLSI Test Symposium, Atlantic City, NJ, USA. Lien externe
Rayapati, V. N., & Kamińska, B. (août 1993). Dynamic reconfiguration schemes for mega bit BiCMOS SRAMs [Communication écrite]. IEEE International Workshop on Memory Testing (MT 1993), San Jose, CA, United states. Lien externe
Rayapati, V. N., & Kamińska, B. (octobre 1993). Multilayer interconnection model for BiCMOS SRAMs [Communication écrite]. Electrical Performance of Electronic Packaging, Monterey, CA, USA. Lien externe
Slamani, M., & Kamińska, B. (novembre 1993). T-BIST: A built-in self-test for analog circuits based on parameter translation [Communication écrite]. 2nd IEEE Asian Test Symposium (ATS 1993), Beijing, China. Lien externe
