Items where Author is "Vialletelle, Philippe"

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Bettayeb, B., Bassetto, S., Vialletelle, P., & Tollenaere, M. (2012). Quality and exposure control in semiconductor manufacturing. Part I: Modelling. International Journal of Production Research, 50(23), 6835-6851. External link

Bettayeb, B., Bassetto, S., Vialletelle, P., & Tollenaere, M. (2012). Quality and exposure control in semiconductor manufacturing. Part II: Evaluation. International Journal of Production Research, 50(23), 6852-6869. External link

Bettayeb, B., Vialletelle, P., Bassetto, S., & Tollenaere, M. (2010, November). Operational risk evaluation and control plan design [Paper]. 13th ARCSIS Technical & Scientific Meeting, Manufacturing Challenges in European Semiconductor Fabs, Rousset, France. Unavailable

Bettayeb, B., Vialletelle, P., Bassetto, S., & Tollenaere, M. (2010, October). Optimized design of control plans based on risk exposure and ressources capabilites [Paper]. International Symposium on Semiconductor Manufacturing (ISSM 2010), Tokyo. Japan. External link

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Shanoun, M. , Vialletelle, P., & Bassetto, S. (2010, November). A dynamic sampling algorithm [Paper]. 13th ARCSIS Technical & Scientific Meeting, Manufacturing Challenges in European Semiconductor Fabs, Rousset, France. Unavailable

Sahnoun, M. , Vialletelle, P., Bassetto, S., Tollenaere, M., & Bastoini, S. (2010, November). Historical wafer-at-risk construction in STMicroelectronics 300mm wafer fab in crollesoptimizing return on inspection through defectivity smart skipping [Paper]. Manufacturing Challenges in European Semiconductor Fabs, Rousset, France. Unavailable

Sahnoun, M., Vialletelle, P., Bastoini, S., Bassetto, S., & Tollenaere, M. (2010, October). Optimized return on inspection through smart-sampling [Paper]. International Symposium on Semiconductor Manufacturing (ISSM 2010), Tokyo, Japan. External link