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Documents dont l'auteur est "Ait Mohamed, Otmane"

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Nombre de documents: 8

Hoque, K. A., Ait Mohamed, O., & Savaria, Y. (2019). Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs. Reliability Engineering and System Safety, 182, 107-119. Lien externe

Kazma, G., Bany Hamad, G., Ait Mohamed, O., & Savaria, Y. (juin 2017). Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe

Hoque, K. A., Ait Mohamed, O., & Savaria, Y. (2017). Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications. Journal of Applied Logic, 25(47-68), 47-68. Lien externe

Bany Hamad, G., Ait Mohamed, O., & Savaria, Y. (2017). Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits. Journal of Electronic Testing: Theory and Applications, 33(5), 607-620. Lien externe

Bany Hamad, G., Ait Mohamed, O., & Savaria, Y. (septembre 2016). SMT-based reliability-aware synthesis for single event transients tolerant combinational circuits [Affiche]. Radiation Effects on Components & Systems Conference (RADECS 2016), Bremen, Germany. Non disponible

Al-bayati, Z., Ait Mohamed, O., Rafay Hasan, S., & Savaria, Y. (décembre 2012). Design of a C-element based clock domain crossing interface [Communication écrite]. 24th International Conference on Microelectronics (ICM 2012), Algiers, Algeria (4 pages). Lien externe

Hoque, K. A., Ait Mohamed, O., Savaria, Y., & Thibeault, C. (octobre 2013). Early analysis of soft error effects for aerospace applications using probabilistic model checking [Communication écrite]. 2nd International Workshop of Formal Techniques for Safety-Critical Systems (FTSCS 2013), Queenstown, New Zealand. Lien externe

Bany Hamad, G., Ait Mohamed, O., Rafay Hasan, S., & Savaria, Y. (mai 2012). Identification of soft error glitch-propagation paths: Leveraging SAT solvers [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of. Lien externe

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