Documents publiés en "2010"

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Berriah, O., Bougataya, M., Lakhssassi, A., Blaquiere, Y., & Savaria, Y. (juin 2010). Thermal analysis of a miniature electronic power device matched to a silicon wafer [Communication écrite]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. Lien externe

Bougataya, M., Berriah, O., Lakhssassi, A., Dahmane, A.-O., Blaquiere, Y., Savaria, Y., Norman, R., & Prytula, R. (décembre 2010). Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit [Communication écrite]. 17th IEEE International Conference on Electronics, Circuits and Systems, Athens, Greece. Lien externe

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Chebli, R., Sawan, M., El-Sankary, K., & Savaria, Y. (2010). High-voltage DMOS integrated circuits using floating-gate protection technique. Analog Integrated Circuits and Signal Processing, 62(2), 223-235. Lien externe

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Gagnon, F., Savaria, Y., Dumais, P., Ammari, M. L., & Thibeault, C. (2010). Multiequalizer unit used for telecommunications has decision unit, which receives corresponding synchronized signals and choose one synchronized signal that matches with predetermined transmission performance criterion signal. (Brevet no US7693490). Lien externe

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Hasan, S. R., Belanger, N., Savaria, Y., & Ahmad, M. O. (2010). Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(8), 2020-2031. Lien externe

Hasan, S. R., Belanger, N., Savaria, Y., & Ahmad, M. O. (2010). Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(10), 2696-707. Lien externe

Hasib, O. A.-T., Sawan, M., & Savaria, Y. (mai 2010). Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. Lien externe

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Marche, D., & Savaria, Y. (2010). Modeling R-2R segmented-ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(1), 31-43. Lien externe

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Tanguay, L.-F., Savaria, Y., & Sawan, M. (juin 2010). A 640 µW frequency synthesizer dedicated to implantable medical microsystems in 90-nm CMOS [Communication écrite]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. Lien externe

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Valorge, O., Blaquiere, Y., & Savaria, Y. (décembre 2010). A spatially reconfigurable fast differential interface for a wafer scale configurable platform [Communication écrite]. 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2010), Athens, Greece. Lien externe

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Zarrabi, H., Al-Khalili, A. J., & Savaria, Y. (mai 2010). An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. Lien externe

Zarrabi, H., Zilic, Z., Savaria, Y., & Al-Khalili, J. A. (2010). On the Efficient Design & Synthesis of Differential Clock Distribution Networks. Dans Wang, Z. (édit.), VLSI (331-352). Disponible