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Ciccarelli, L., & Lodi, A. (2010). T-switch buffer, in particular for FPGA architectures. (Brevet no US7683674). Lien externe
Ciccarelli, L., Chiesa, C., Lodi, A., Giansante, R., Toma, M., & Campi, F. (2008). Switch block and corresponding switch matrix, in particular for FPGA architectures. (Brevet no US7463055). Lien externe
Cappelli, A., Ciccarelli, L., Lodi, A., Toma, M., & Campi, F. (2007). Architecture for a connection block in reconfigurable gate arrays. (Brevet no US7193437). Lien externe
Campi, F., Deledda, A., Pizzotti, M., Ciccarelli, L., Rolandi, P., Mucci, C., Lodi, A., Vitkovski, A., & Vanzolini, L. (avril 2007). A dynamically adaptive DSP for heterogeneous reconfigurable platforms [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice Acropolis, France. Lien externe
Ciccarelli, L., Loparco, D., Innocenti, M., Lodi, A., Mucci, C., & Rolandi, P. (septembre 2006). A low-power routing architecture optimized for deep sub-micron FPGAs [Communication écrite]. IEEE Custom Integrated Circuits Conference (CICC 2006), San Jose, CA, United states. Lien externe
Cappelli, A., Lodi, A., Bocchi, M., Mucci, C., Innocenti, M., De, B. C., Ciccarelli, L., Giansante, R., Deledda, A., Campi, F., Toma, M., & Guerrieri, R. (février 2005). XiSystem: A XiRisc-based SoC with a reconfigurable IO module [Communication écrite]. IEEE International Solid-State Circuits Conference (ISSCC 2005), San Francisco, CA, United states. Lien externe
Ciccarelli, L., Lodi, A., & Canegallo, R. (octobre 2004). Low leakage circuit design for FPGAs [Communication écrite]. IEEE Custom Integrated Circuits Conference (CICC 2004), Orlando, FL, United states. Lien externe
Lodi, A., Mucci, C., Bocchi, M., Cappelli, A., De Dominicis, M., & Ciccarelli, L. (août 2006). A multi-context pipelined array for embedded systems [Communication écrite]. International Conference on Field Programmable Logic and Applications (FPL 2006), Madrid, Spain. Lien externe
Lodi, A., Ciccarelli, L., & Giansante, R. (février 2005). Combining low-leakage techniques for FPGA routing design [Communication écrite]. 13th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2005), Monterey, CA, United states. Lien externe
Lodi, A., Ciccarelli, L., Mucci, C., Giansante, R., Cappelli, A., & Toma, M. (avril 2005). An embedded reconfigurable datapath for SoC [Communication écrite]. 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), Napa, CA, United states. Lien externe
Lodi, A., Ciccarelli, L., Loparco, D., Canegallo, R., & Guerrieri, R. (septembre 2005). Low leakage design of LUT-based FPGAs [Communication écrite]. 31st European Solid-State Circuits Conference (ESSCIRC 2005), Grenoble, France. Lien externe
Lodi, A., Giansante, R., Chiesa, C., Ciccarelli, L., Toma, M., & Campi, F. (février 2004). Routing architecture for multi-context FPGAs [Communication écrite]. 12th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2004), Monterey, CA, USA. Lien externe
Lodi, A., Ciccarelli, L., Cappelli, A., Campi, F., & Toma, M. (février 2003). Decoder-based multi-context interconnect architecture [Communication écrite]. IEEE Computer Society Annual Symposium on VLSI: New Trends and Technologies for Vlsi Systems Design (ISVLSI 2003), Tampa, FL, United states. Lien externe
Mucci, C., Bocchi, M., Gagliardi, P., Ciccarelli, L., Lodi, A., Toma, M., & Campi, F. (mai 2006). A case-study on multimedia applications for the XiRisc reconfigurable processor [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Kos, Greece. Lien externe
