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A low-power routing architecture optimized for deep sub-micron FPGAs

Luca Ciccarelli, Domenico Loparco, Massimiliano Innocenti, Andrea Lodi, Claudio Mucci and Pierluigi Rolandi

Paper (2006)

Document published while its authors were not affiliated with Polytechnique Montréal

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PolyPublie URL: https://publications.polymtl.ca/23218/
Conference Title: IEEE Custom Integrated Circuits Conference (CICC 2006)
Conference Location: San Jose, CA, United states
Conference Date(s): 2006-09-10 - 2006-09-13
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/cicc.2006.320889
Official URL: https://doi.org/10.1109/cicc.2006.320889
Date Deposited: 18 Apr 2023 15:17
Last Modified: 05 Apr 2024 11:08
Cite in APA 7: Ciccarelli, L., Loparco, D., Innocenti, M., Lodi, A., Mucci, C., & Rolandi, P. (2006, September). A low-power routing architecture optimized for deep sub-micron FPGAs [Paper]. IEEE Custom Integrated Circuits Conference (CICC 2006), San Jose, CA, United states. https://doi.org/10.1109/cicc.2006.320889

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