Andrea Lodi, Luca Ciccarelli, Domenico Loparco, Roberto Canegallo and Roberto Guerrieri
Paper (2005)
Document published while its authors were not affiliated with Polytechnique Montréal
An external link is available for this itemAdditional Information: | ESSCIRC 2005: 31st European Solid-State Circuits Conference, September 12, 2005 - September 16, 2005 |
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ISBN: | 0780392051 |
PolyPublie URL: | https://publications.polymtl.ca/23916/ |
Conference Title: | 31st European Solid-State Circuits Conference (ESSCIRC 2005) |
Conference Location: | Grenoble, France |
Conference Date(s): | 2005-09-12 - 2005-09-16 |
Publisher: | Institute of Electrical and Electronics Engineers Computer Society |
DOI: | 10.1109/esscir.2005.1541582 |
Official URL: | https://doi.org/10.1109/esscir.2005.1541582 |
Date Deposited: | 18 Apr 2023 15:18 |
Last Modified: | 08 Apr 2025 02:12 |
Cite in APA 7: | Lodi, A., Ciccarelli, L., Loparco, D., Canegallo, R., & Guerrieri, R. (2005, September). Low leakage design of LUT-based FPGAs [Paper]. 31st European Solid-State Circuits Conference (ESSCIRC 2005), Grenoble, France. https://doi.org/10.1109/esscir.2005.1541582 |
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