 | Up a level |
Collaboration networkThis graph maps the connections between all the collaborators of {}'s publications listed on this page.
Each link represents a collaboration on the same publication. The thickness of the link represents the number of collaborations.
Use the mouse wheel or scroll gestures to zoom into the graph.
You can click on the nodes and links to highlight them and move the nodes by dragging them.
Hold down the "Ctrl" key or the "⌘" key while clicking on the nodes to open the list of this person's publications.
Word cloudA word cloud is a visual representation of the most frequently used words in a text or a set of texts. The words appear in different sizes, with the size of each word being proportional to its frequency of occurrence in the text. The more frequently a word is used, the larger it appears in the word cloud. This technique allows for a quick visualization of the most important themes and concepts in a text.
In the context of this page, the word cloud was generated from the publications of the author {}. The words in this cloud come from the titles, abstracts, and keywords of the author's articles and research papers. By analyzing this word cloud, you can get an overview of the most recurring and significant topics and research areas in the author's work.
The word cloud is a useful tool for identifying trends and main themes in a corpus of texts, thus facilitating the understanding and analysis of content in a visual and intuitive way.
Abderrahman, A., Cerny, E., & Kamińska, B. (1999). Worst Case Tolerance Analysis and Clp-Based Multifrequency Test Generation for Analog Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(3), 332-345. External link
Abderrahman, A., Cerny, E., & Kamińska, B. (1997, April). CLP-based multifrequency test generation for analog circuits [Paper]. 1997 15th VLSI Test Symposium, Monterey, CA, USA. External link
Abderrahman, A., Cerny, E., & Kamińska, B. (1996). Optimization-based multifrequency test generation for analog circuits. Journal of Electronic Testing: Theory and Applications (JETTA), 9(1-2), 59-73. External link
Boubezari, S., Cerny, E., Kamińska, B., & Nadeau-Dostie, B. (1999). Testability Analysis and Test-Point Insertion in Rtl Vhdl Specifications for Scan-Based Bist. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(9), 1327-1340. External link
Cerny, E., Bois, G., Bourgault, M., Demers, L.-P., Fauvel, S., Jacques, P., Mailhot, P., & Roy, C. (1989). Integration of VLSI CAD tools based on cell-objects : the CHESHIRE system. In Zobrist, G. W. (ed.), Progress in computer-aided VLSI Design : tools (pp. 235-272). External link
Cerny, E., Aboulhamid, E. M., Bois, G., & Cloutier, J. (1988). Built-in self-test of a CMOS ALU. IEEE Design & Test of Computers, 5(4), 38-48. External link
Kabbaj, A., Cerny, E., Dagenais, M., & Bouthillier, F. (1991, February). Design by similarity using transaction modeling and statistical techniques [Paper]. European Conference on Design Automation (EDAC 1991), Amsterdam, Netherlands. External link
Martineau, J.-L., Bois, G., & Cerny, E. (1992, March). Automatic jog insertion for 2D mask compaction: a global optimization perspective [Paper]. European Conference on Design Automation (EDAC 1992), Brussels, Belgium. External link
