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Berrima, S., Blaquiere, Y., & Savaria, Y. (août 2017). Sub-ps resolution programmable delays implemented in a Xilinx FPGA [Communication écrite]. 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Boston, MA. Lien externe
Berriah, O., Bougataya, M., Lakhssassi, A., Blaquiere, Y., & Savaria, Y. (juin 2010). Thermal analysis of a miniature electronic power device matched to a silicon wafer [Communication écrite]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. Lien externe
Basile-Bellavance, Y., Blaquiere, Y., & Savaria, Y. (juin 2009). Faults diagnosis methodology for the WaferNet interconnection network [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
Basile-Bellavance, Y., Lepercq, E., Blaquiere, Y., & Savaria, Y. (août 2008). Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL [Communication écrite]. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008). Lien externe
Blaquiere, Y., Dagenais, M., & Savaria, Y. (1996). Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), 244-255. Lien externe
Laflamme-Mayer, N., Valorge, O., Blaquiere, Y., & Sawan, M. (juin 2010). A Low-Power, Small-Area Voltage Reference Array for a Wafer-Scale Prototyping Platform [Communication écrite]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. Lien externe
Lepercq, E., Blaquiere, Y., Norman, R., & Savaria, Y. (mai 2009). Workflow for an electronic configurable prototyping system [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan. Lien externe
Nguyen, H. H., Guillemot, M., Savaria, Y., & Blaquiere, Y. (octobre 2012). A new approach for pin detection for an electronic system prototyping reconfigurable platform [Communication écrite]. 23rd IEEE International Symposium on Rapid System Prototyping (RSP 2012), Tampere, Finland. Lien externe
Norman, R., Lepercq, E., Blaquiere, Y., Valorge, O., Basile-Bellavance, Y., Prytula, R., & Savaria, Y. (juin 2008). An interconnection network for a novel reconfigurable circuit board [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Sion, G., Blaquiere, Y., & Savaria, Y. (juillet 2015). Defect diagnosis algorithms for a field programmable interconnect network embedded in a very large area integrated circuit [Communication écrite]. 21st International On-Line Testing Symposium (IOLTS 2015), Athena Pallas, Greece. Lien externe
Thibeault, C., Pichette, S., Audet, Y., Savaria, Y., Rufenacht, H., Gloutnay, E., Blaquiere, Y., Moupfouma, F., & Batani, N. (2012). On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations. IEEE Transactions on Nuclear Science, 59(6), 2959-65. Lien externe
