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Evaluation of delay mismatch due to process variations in CMOS integrated circuits

Bo Zhou

Masters thesis (2006)

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Cite this document: Zhou, B. (2006). Evaluation of delay mismatch due to process variations in CMOS integrated circuits (Masters thesis, École Polytechnique de Montréal). Retrieved from https://publications.polymtl.ca/7842/
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Motivation -- Thesis goal -- Organization of thesis -- Process variations in CMOS integrated circuits -- Sources of process variations -- Effects of process variations on circuit performances -- Statistical analysis in CADENCE -- Measuring single cell delay and delay mismatch -- State of the art -- Simple modified RO test structure -- Improved modified RO test structure -- Delay mismatch analysis -- Validation -- Digital control circuit -- Design implementation -- Design consideration -- Design flow -- RO layout structures -- Digital part realization -- Test chip on top-level -- Post-layout simulation results -- Test strategy -- Printed circuit board for testing -- Test procedure -- Measuring accurancy -- Chip analysis.

Uncontrolled Keywords

MOS complémentaires; Circuits intégrés numériques; Pannes temporelles (Semi-conducteurs)

Open Access document in PolyPublie
Additional Information: Le fichier PDF de ce document a été produit par Bibliothèque et Archives Canada selon les termes du programme Thèses Canada https://canada.on.worldcat.org/oclc/275811933
Department: Département de génie électrique
Date Deposited: 04 Aug 2021 11:05
Last Modified: 25 Aug 2021 14:58
PolyPublie URL: https://publications.polymtl.ca/7842/


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