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Bendaoudi, H., Cheriet, F., Manraj, A., Ben Tahar, H., & Langlois, J. M. P. (2018). Flexible architectures for retinal blood vessel segmentation in high-resolution fundus images. Journal of Real-Time Image Processing, 15(1), 31-42. Lien externe
Mosleh, A., Elmi Sola, Y., Zargari, F., Onzon, E., & Langlois, J. M. P. (2018). Explicit ringing removal in image deblurring. IEEE Transactions on Image Processing, 27(2), 580-593. Lien externe
Vakili, S., Langlois, J. M. P., Savaria, Y., & Manjikian, N. (2018). Enhanced Bloom filter utilisation scheme for string matching using a splitting approach. IET Communications, 12(7), 868-875. Lien externe
Abdelsalam, A. M., Boulet, F., Demers, G., Langlois, J. M. P., & Cheriet, F. (décembre 2018). An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNs [Communication écrite]. International Conference on ReConFigurable Computing and FPGAs (ReConFig 2018), Cancun, Mexico (6 pages). Lien externe
Abdelsalam, A. M., Elsheikh, A., David, J. P., & Langlois, J. M. P. (octobre 2018). POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal. Lien externe
Ahmadi, M., Vakili, S., Langlois, J. M. P., & Gross, W. J. (juin 2018). Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy [Communication écrite]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. Lien externe
Chidambaram, S., Riviello, A., Langlois, J. M. P., & David, J. P. (octobre 2018). Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal. Lien externe
Léonardon, M., Leroux, C., Binet, D., Langlois, J. M. P., Jégo, C., & Savaria, Y. (mai 2018). Custom low power processor for polar decoding [Communication écrite]. IEEE International Symposium on Circuits & Systems (ISCAS 2018), Florence, Italy. Lien externe
Santiago da Silva, J., Boyer, F.-R., & Langlois, J. M. P. (février 2018). P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), Monterey, California, USA. Lien externe
Santiago da Silva, J., Boyer, F.-R., Chiquette, L.-O., & Langlois, J. M. P. (juin 2018). Extern objects in P4: an ROHC compressing scheme case study [Communication écrite]. IEEE Conference on Network Softwarization (NetSoft 2018), Montréal, Québec. Lien externe
Stimpfling, T., Langlois, J. M. P., Bélanger, N., & Savaria, Y. (mai 2018). A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis [Communication écrite]. 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018), Washington, D.C.. Lien externe
