Documents publiés en "1997"

A

Antaki, B., Patenaude, S., Trognon, L., & Savaria, Y. (juin 1997). Study on split-output TSPC CMOS circuits [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong. Lien externe

B

Bélanger, N., Antaki, B., & Savaria, Y. (juillet 1997). An algorithm for fast array transfers [Communication écrite]. 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada. Non disponible

Bois, G., Bosi, B., & Savaria, Y. (janvier 1997). High performance reconfigurable coprocessor for digital signal processing [Communication écrite]. 14th Annual International Conference of the Mentor Graphics Users' Group, Portland, Oregon. Non disponible

G

Gagnon, Y., Meunier, M., Savaria, Y., & Thibeault, C. (octobre 1997). Mathematical cost model for redundant multi-processor arrays [Communication écrite]. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France. Publié dans Journal of Microelectronic Systems Integration, 5(4). Non disponible

Gagnon, Y., Savaria, Y., Meunier, M., & Thibeault, C. (octobre 1997). Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1997), Paris, Fr. Lien externe

Granger, É., Savaria, Y., Blaquière, Y., Cantin, M.-A., & Lavoie, P. (1997). A VLSI architecture for fast clustering with fuzzy ART neural networks. Journal of Microelectronic Systems Integration, 5(1), 3-18. Non disponible

H

Hrytzak, R., Savaria, Y., & Goslin, G. (janvier 1997). Reconfigurable computing greatly simplifies system development [Communication écrite]. DSP World Spring Design Conference. Non disponible

K

Kafrounni, M., Thibeault, C., & Savaria, Y. (janvier 1997). Cost model for VLSI/MCM systems [Communication écrite]. IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France. Lien externe

Khali, H., Savaria, Y., & Houle, J.-L. (juillet 1997). Computational limits of homogeneous acceleration using lookup tables [Communication écrite]. 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada. Non disponible

L

Lavoie, P., Crespo, J. F., & Savaria, Y. (juin 1997). Multiple categorization using fuzzy ART [Communication écrite]. IEEE International Conference on Neural Networks (ICNN 1997), Houston, TX, USA. Lien externe

N

Nekili, M., Bois, G., & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174. Lien externe

P

Pera, F., Savaria, Y., & Bois, G. (juin 1997). Time delay measurement methods for integrated transmission lines and high speed cells characterization [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong. Lien externe