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Boyer, F.-R., Epassa, H. G., Pontikakis, B., Savaria, Y., & Ling, W. (juin 2004). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (juin 2008). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Pontikakis, B., Boyer, F.-R., Savaria, Y., & Bui, H. T. (août 2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation [Communication écrite]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007). Lien externe
Pontikakis, B., Boyer, F.-R., & Savaria, Y. (mai 2006). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. Lien externe
Pontikakis, B., Boyer, F.-R., & Savaria, Y. (juillet 2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period [Communication écrite]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. Lien externe
