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Amadou, M., Le Beux, S., Nicolescu, G., & O'Connor, I. (2009, December). Functional mapping for nanodevice-based architectures [Paper]. International Conference on Microelectronics (ICM 2009), Marrakech, Morocco. External link
Briere, M., Girodias, B., Bouchebaba, Y., Nicolescu, G., Mieyeville, F., Gafflot, F., & O'Connor, I. (2007, August). Architectural exploration of optical and electrical interconnects in MPSoC [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montreal, QC, Canada (4 pages). External link
Briere, M., Girodias, B., Bouchebaba, Y., Nicolescu, G., Mieyeville, F., Gaffiot, F., & O'Connor, I. (2007, April). System level assessment of an optical NoC in an MPSoC platform [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice Acropolis, France. External link
Fourmigue, A., Beltrame, G., Nicolescu, G., Aboulhamid, E. M., & O'Connor, I. (2011, March). Multi-granularity thermal evaluation of 3D MPSoC architectures [Paper]. 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France. External link
Gheorghe, L., Nicolescu, G., & O'Connor, I. (2009, October). Modeling and Formal Verification of a Passive Optical Network on Chip Behavior [Paper]. 3rd International Workshop on Multi-Paradigm Modeling (MPM 2009), Denver, CO, USA (11 pages). Published in Electronic Communications of the EASST, 21. External link
Gheorghe, L., Nicolescu, G., & O'Connor, I. (2016). Formalization for formal verification of an optical network-on-chip using DEVS. In Wainer, G., & Mosterman, P. J. (eds.), Discrete-Event Modeling and Simulation: Theory and Applications (pp. 293-306). External link
Gaillardon, P.-E., Clermidy, F., O'Connor, I., Liu, J., Amadou, M., & Nicolescu, G. (2011). Matrix nanodevice-based logic architectures and associated functional mapping method. ACM Journal on Emerging Technologies in Computing Systems, 7(1), 1-23. External link
Hui, L., Le Beux, S., Nicolescu, G., & O'Connor, I. (2015, January). Energy-efficient optical crossbars on chip with multi-layer deposited silicon [Paper]. 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba, Japan. External link
Hui, L., Fourmigue, A., Le Beux, S., Letartre, X., O'Connor, I., & Nicolescu, G. (2015, March). Thermal aware design method for VCSEL-based on-chip optical interconnect [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2015), Grenoble, France. External link
Li, H., Fourmigue, A., Le Beux, S., O'Connor, I., & Nicolescu, G. (2016, March). A thermal-Aware Laser Tuning Approach for Silicon Photonic Interconnects [Paper]. 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop 2016), Dresden, Germany. Unavailable
Li, H., Fourmigue, A., Le Beux, S., O'Connor, I., & Nicolescu, G. (2016). Towards Maximum Energy Efficiency in Nanophotonic Interconnects with Thermal-Aware On-Chip Laser Tuning. IEEE Transactions on Emerging Topics in Computing, 6(3), 343-356. External link
Le Beux, S., Li, H., O'Connor, I., Cheshmi, K., Liu, X., Trajković, J., & Nicolescu, G. (2014, March). Chameleon: Channel efficient optical network-on-chip [Paper]. 17th Design, Automation and Test in Europe (DATE 2014), Dresden, Germany. External link
Le Beux, S., Li, H., Nicolescu, G., Trajković, J., & O'Connor, I. (2014). Optical crossbars on chip, a comparative study based on worst-case losses. Concurrency Computation Practice and Experience, 26(15), 2492-2503. External link
Le Beux, S., Li, H., Nicolescu, G., & O'Connor, I. (2014, May). A reconfigurable optical network on chip for streaming applications [Paper]. 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC 2014), Montpellier, France (2 pages). External link
Le Beux, S., O'Connor, I., Li, Z., Letartre, X., Monat, C., Trajkovic, J., & Nicolescu, G. (2013, May). Potential and pitfalls of silicon photonics computing and interconnect [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, China. External link
Le Beux, S., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2013). Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocessors and Microsystems, 37(1), 87-98. External link
Le Beux, S., Trajković, J., O'Connor, I., & Nicolescu, G. (2011, October). Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC) [Paper]. 19th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2011), Kowloon, Hong kong. External link
Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2011, March). Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology [Paper]. 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France. External link
Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2010). Multi-optical network-on-chip for large scale MPSoC. IEEE Embedded Systems Letters, 2(3), 77-80. External link
Nicolescu, G., O'Connor, I., & Piguet, C. (2012). Design technology for heterogeneous embedded systems. External link
O'Connor, I., & Nicolescu, G. (eds.) (2012). Integrated Optical Interconnect Architectures for Embedded System. (1st ed.). External link
O'Connor, I., Liu, J., Kotb, J., Yakymets, N., Daviot, R., Navarro, D., Gaillardon, P.-E., Clermidy, F., Amadou, M., & Nicolescu, G. (2009, October). Emerging Technologies and Nanoscale Computing Fabrics [Paper]. 17th IFIP WH 10.5/IEEE International Conference on Very Large Scale Integration (BLSI-SoC 2009), Florianopolis, Brazil (20 pages). External link
O'Connor, I., Mieyeville, F., Gaffiot, F., Scandurra, A., & Nicolescu, G. (2008, October). Can integrated photonics solve MPSoC interconnect issues? [Paper]. 25th International VLSI Multilevel Interconnection Conference (VMIC 2008), Fremont, CA, United states. Unavailable
Wang, Y., Aouina, A., Li, H., O'Connor, I., Nicolescu, G., & Le Beux, S. (2019). Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(3), 742-746. External link
