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Ardakani, A., Condo, C., Ahmadi, M., & Gross, W. J. (2018). An architecture to accelerate convolution in deep neural networks. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(4), 1349-1362. Lien externe
Ahmadi, M., Vakili, S., Langlois, J. M. P., & Gross, W. J. (juin 2018). Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy [Communication écrite]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. Lien externe
Ardakani, A., Leduc-Primeau, F., Onizawa, N., Hanyu, T., & Gross, W. J. (2017). VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(10), 2688-2699. Lien externe
Ardakani, A., Leduc-Primeau, F., & Gross, W. J. (mars 2016). Hardware implementation of FIR/IIR digital filters using integral stochastic computation [Communication écrite]. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2016), Shanghai, China. Lien externe
Ardakani, A., Leduc-Primeau, F., Onizawa, N., Hanyu, T., & Gross, W. J. (septembre 2016). VLSI implementation of deep neural networks using integral stochastic computing [Communication écrite]. 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC 2016), Brest, France. Lien externe
Boga, K., Leduc-Primeau, F., Onizawa, N., Matsumiya, K., Hanyu, T., & Gross, W. J. (2016). A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception. Journal of Signal Processing Systems, 90(5), 709-725. Lien externe
Boga, K., Onizawa, N., Leduc-Primeau, F., Matsumiya, K., Hanyu, T., & Gross, W. J. (octobre 2015). Stochastic implementation of the disparity energy model for depth perception [Communication écrite]. IEEE Workshop on Signal Processing Systems (SiPS 2015), Hangzhou, China (6 pages). Lien externe
Condo, C., Giard, P., Leduc-Primeau, F., Sarkis, G., & Gross, W. J. (2018). A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(4), 1420-1431. Lien externe
Condo, C., Leduc-Primeau, F., Sarkis, G., Giard, P., & Gross, W. J. (décembre 2016). Stall pattern avoidance in polynomial product codes [Communication écrite]. IEEE Global Conference on Signal and Information Processing (GlobalSIP 2016), Washington, D.C.. Lien externe
Gross, W. J., Leduc-Primeau, F., Hemati, S., & Mannor, S. (2014). Method and system for decoding. (Brevet no US8898537). Lien externe
Gross, W. J., Hemati, S., Mannor, S., Naderi, A., & Leduc-Primeau, F. (2014). Method and system for decoding. (Brevet no US8677227). Lien externe
Hemati, S., Leduc-Primeau, F., & Gross, W. J. (2016). A Relaxed Min-Sum LDPC Decoder With Simplified Check Nodes. IEEE Communications Letters, 20(3), 422-425. Lien externe
Leduc-Primeau, F., Hemati, S., Gaudet, V. C., & Gross, W. J. (2019). Stochastic Decoding of Error-Correcting Codes. Dans Gross, W. J., & Gaudet, V. C. (édit.), Stochastic Computing: Techniques and Applications (201-215). Lien externe
Leduc-Primeau, F., Kschischang, F. R., & Gross, W. J. (2018). Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations. IEEE Transactions on Communications, 66(3), 932-946. Lien externe
Leduc-Primeau, F., Gripon, V., Rabbat, M. G., & Gross, W. J. (2016). Fault-Tolerant Associative Memories Based on c-Partite Graphs. IEEE Transactions on Signal Processing, 64(4), 829-841. Lien externe
Leduc-Primeau, F., & Gross, W. J. (septembre 2016). Finite-length quasi-synchronous LDPC decoders [Communication écrite]. 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC 2016), Brest, France. Lien externe
Leduc-Primeau, F., Kschischang, F. R., & Gross, W. J. (juin 2015). Energy optimization of LDPC decoder circuits with timing violations [Communication écrite]. IEEE International Conference on Communications (ICC 2015), London, UK. Lien externe
Leduc-Primeau, F., Gaudet, V. C., & Gross, W. J. (2015). Stochastic Decoders for LDPC Codes. Dans Chavet, C., & Coussy, P. (édit.), Advanced Hardware Design for Error Correcting Codes (105-128). Lien externe
Leduc-Primeau, F., Gripon, V., Rabbat, M. G., & Gross, W. J. (mai 2014). Cluster-based associative memories built from unreliable storage [Communication écrite]. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2014), Florence, Italy. Lien externe
Leduc-Primeau, F., Hemati, S., Mannor, S., & Gross, W. J. (2013). Relaxed Half-Stochastic Belief Propagation. IEEE Transactions on Communications, 61(5), 1648-1659. Lien externe
Leduc-Primeau, F., Hemati, S., Mannor, S., & Gross, W. J. (2012). Dithered Belief Propagation Decoding. IEEE Transactions on Communications, 60(8), 2042-2047. Lien externe
Leduc-Primeau, F., & Gross, W. J. (octobre 2012). Faulty Gallager-B decoding with optimal message repetition [Communication écrite]. 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton 2012), Monticello, IL. Lien externe
Leduc-Primeau, F., Raymond, A. J., Giard, P., Cushon, K., Thibeault, C., & Gross, W. J. (octobre 2012). High-throughput LDPC decoding using the RHS algorithm [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany (6 pages). Lien externe
Leduc-Primeau, F., Hemati, S., Mannor, S., & Gross, W. J. (décembre 2010). Lowering Error Floors Using Dithered Belief Propagation [Communication écrite]. IEEE Global Telecommunications Conference (GLOBECOM 2010), Miami, FL. Lien externe
Leduc-Primeau, F., Hemati, S., Gross, W. J., & Mannor, S. (novembre 2009). A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes [Communication écrite]. IEEE Global Telecommunications Conference (GLOBECOM 2009), Honolulu, HI (6 pages). Lien externe
Naderi, A., Mannor, S., Sawan, M., & Gross, W. J. (2011). Delayed stochastic decoding of LDPC codes. IEEE Transactions on Signal Processing, 59(11), 5617-5626. Lien externe
