Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations

François Leduc-Primeau, Frank R. Kschischang and Warren J. Gross

Article (2018)

Document published while its authors were not affiliated with Polytechnique Montréal

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Research Center:	GR2M - Microelectronics and Microsystems Research Group
PolyPublie URL:	https://publications.polymtl.ca/41654/
Journal Title:	IEEE Transactions on Communications (vol. 66, no. 3)
Publisher:	IEEE
DOI:	10.1109/tcomm.2017.2778247
Official URL:	https://doi.org/10.1109/tcomm.2017.2778247
Date Deposited:	18 Apr 2023 15:03
Last Modified:	08 Apr 2025 07:06

Cite in APA 7:	Leduc-Primeau, F., Kschischang, F. R., & Gross, W. J. (2018). Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations. IEEE Transactions on Communications, 66(3), 932-946. https://doi.org/10.1109/tcomm.2017.2778247
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