<  Back to the Polytechnique Montréal portal

Items where Author is "Chabini, Noureddine"

Up a level
Export as [feed] Atom [feed] RSS 1.0 [feed] RSS 2.0
Jump to: C | G
Number of items: 6.

C

Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (2003). Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(3), 346-351. External link

Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (2003, April). Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs [Paper]. Great Lakes Symposium on VLSI (GLSVLSI 2003), Washington, D. C., USA. External link

G

Gao, S., Al-Khalili, D., Langlois, J. M. P., & Chabini, N. (2017). Efficient realization of BCD multipliers using FPGAs. International Journal of Reconfigurable Computing, 2017, 1-12. Available

Gao, S., Al-Khalili, D., Langlois, J. M. P., & Chabini, N. (2017, April). Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier [Paper]. 30th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2017), Windsor, ON, Canada (6 pages). External link

Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2010). FPGA-based efficient design approaches for large size two's complement squarers. Journal of Signal Processing Systems, 58(1), 3-15. External link

Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2005, November). Optimized multipliers for large unsigned integers [Paper]. NORCHIP Conference, Oulu, Finlande. External link

List generated on: Sun Jun 23 18:47:35 2024 EDT