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Collaboration networkThis graph maps the connections between all the collaborators of {}'s publications listed on this page.
Each link represents a collaboration on the same publication. The thickness of the link represents the number of collaborations.
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Word cloudA word cloud is a visual representation of the most frequently used words in a text or a set of texts. The words appear in different sizes, with the size of each word being proportional to its frequency of occurrence in the text. The more frequently a word is used, the larger it appears in the word cloud. This technique allows for a quick visualization of the most important themes and concepts in a text.
In the context of this page, the word cloud was generated from the publications of the author {}. The words in this cloud come from the titles, abstracts, and keywords of the author's articles and research papers. By analyzing this word cloud, you can get an overview of the most recurring and significant topics and research areas in the author's work.
The word cloud is a useful tool for identifying trends and main themes in a corpus of texts, thus facilitating the understanding and analysis of content in a visual and intuitive way.
Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (2003). Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(3), 346-351. External link
Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (2003, April). Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs [Paper]. Great Lakes Symposium on VLSI (GLSVLSI 2003), Washington, D. C., USA. External link
Gao, S., Al-Khalili, D., Langlois, J. M. P., & Chabini, N. (2017). Efficient realization of BCD multipliers using FPGAs. International Journal of Reconfigurable Computing, 2017, 1-12. Available
Gao, S., Al-Khalili, D., Langlois, J. M. P., & Chabini, N. (2017, April). Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier [Paper]. 30th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2017), Windsor, ON, Canada (6 pages). External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2010). FPGA-based efficient design approaches for large size two's complement squarers. Journal of Signal Processing Systems, 58(1), 3-15. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2005, November). Optimized multipliers for large unsigned integers [Paper]. NORCHIP Conference, Oulu, Finlande. External link
