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Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (2003). Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(3), 346-351. External link
Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (2003, April). Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs [Paper]. Great Lakes Symposium on VLSI (GLSVLSI 2003), Washington, D. C., USA. External link
Chabini, N., Aboulhamid, E. M., Chabini, I., & Savaria, Y. Minimizing the Number of Phases in Clocked Digital Designs Derived Using Modulo Scheduling Techniques [Paper]. Icm 2002: 14th International Conference on Microelectronics. External link
Chabini, N., Aboulhamid, E. M., Chabini, I., & Savaria, Y. (2002, August). Minimizing the number of registers and the number of phases in synchronous digital designs with minimal clock period [Paper]. 45th Midwest Symposium on Circuits and Systems (MWSCAS 2002), Tulsa, OK, USA. External link
Chabini, N., Aboulhamid, M., & Savaria, Y. (2001, January). Determining schedules for reducing power consuption using mulyiple supply voltages [Paper]. International Conference on Computer Design (ICCD 2001), Austin, Texas. External link
Chabini, N., Aboulhamid, E. M., & Savaria, Y. (2001, August). Efficient Methods for Reducing Register and Phase Requirements for Synchronous Circuits Derived Using Software Pipelining Techniques [Paper]. European Conference on Circuit Theory and Design (ECCTD 2001), Espoo, Finland. Unavailable
Chabini, N., & Savaria, Y. (2001, September). Methods for optimizating register placement in synchronous circuits derived using software pipelining techniques [Paper]. 14th International Symposium on System Synthesis (ISSS 2001), Montréal, Québec. External link
Chabini, N., & Savaria, Y. (2001, September). Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques [Paper]. 14th International Symposium on System Synthesis (ISSS 2001), Montréal, QC, Canada. External link
Chabini, N., Aboulhamid, E. M., & Savaria, Y. (2001, January). Minimizing registe requirements for synchronous circuits derived using software pipelining techniques [Paper]. 13th International Conference on Microelectronics (ICM 2001), Rabat, Maroc. External link
Chabini, N., Aboulhamid, E. M., & Savaria, Y. (2001, April). Reducing register and phase requirements for synchronous circuits derived using software pipelining techniques [Paper]. IEEE Computer Society Workshop on VLSI (WVLSI 2001), Orlando, FL, United states. External link
Chabini, N., Bennour, I. E., Aboulhamid, E. M., & Savaria, Y. (1998, January). Static method for system performance estimation [Paper]. 10th International Conference on Microelectronics. External link
Gao, S., Al-Khalili, D., Langlois, J. M. P., & Chabini, N. (2017). Efficient realization of BCD multipliers using FPGAs. International Journal of Reconfigurable Computing, 2017, 1-12. Available
Gao, S., Al-Khalili, D., Langlois, J. M. P., & Chabini, N. (2017, April). Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier [Paper]. 30th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2017), Windsor, ON, Canada (6 pages). External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2010). FPGA-based efficient design approaches for large size two's complement squarers. Journal of Signal Processing Systems, 58(1), 3-15. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007, July). FPGA-based efficient design approach for large-size two's complement squarers [Paper]. IEEE International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, September). Efficient FPGA-based realization of complex squarer and complex conjugate using embedded mulitpliers [Paper]. IEEE International SOC Conference (SOCC 2006), Austin, TX, USA. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, June). Efficient realization of large integers multipliers and squarers [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, March). An optimized design approach for squaring large integers using embedded hardwired multipliers [Paper]. ACS/IEEE International Conference on Computer Systems and Applications. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2005, November). Optimized multipliers for large unsigned integers [Paper]. NORCHIP Conference, Oulu, Finlande. External link
