Minimizing the number of registers and the number of phases in synchronous digital designs with minimal clock period

Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini and Yvon Savaria

Paper (2002)

An external link is available for this item

Department:	Department of Electrical Engineering
ISBN:	0780375238
PolyPublie URL:	https://publications.polymtl.ca/75658/
Conference Title:	45th Midwest Symposium on Circuits and Systems (MWSCAS 2002)
Conference Location:	Tulsa, OK, USA
Conference Date(s):	2002-08-04 - 2002-08-07
Publisher:	Institute of Electrical and Electronics Engineers
DOI:	10.1109/mwscas.2002.1187273
Official URL:	https://doi.org/10.1109/mwscas.2002.1187273
Date Deposited:	06 May 2026 10:11
Last Modified:	06 May 2026 10:11

Cite in APA 7:	Chabini, N., Aboulhamid, E. M., Chabini, I., & Savaria, Y. (2002, August). Minimizing the number of registers and the number of phases in synchronous digital designs with minimal clock period [Paper]. 45th Midwest Symposium on Circuits and Systems (MWSCAS 2002), Tulsa, OK, USA. https://doi.org/10.1109/mwscas.2002.1187273
APA 7 (HTML)ASCII CitationAtomBibTeXDOIsDublin CoreEndNote (.ENW)MARC (ISO 2709/UTF-8) (.MRC)MARC (UTF-8) (.MRK8)MARC XMLMPEG-21 DIDLMultiline CSVOAI-ORE Resource Map (Atom Format)OPENAIREOpenURL ContextObjectOpenURL ContextObject in SpanRDF+N-TriplesRDF+N3RDF+XMLReferReference Manager (.RIS)Simple Metadata

Statistics

Repository Staff Only