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Sahnoun, M. , Vialletelle, P., Bassetto, S., Tollenaere, M., & Bastoini, S. (novembre 2010). Historical wafer-at-risk construction in STMicroelectronics 300mm wafer fab in crollesoptimizing return on inspection through defectivity smart skipping [Communication écrite]. Manufacturing Challenges in European Semiconductor Fabs, Rousset, France. Non disponible
Sahnoun, M., Vialletelle, P., Bastoini, S., Bassetto, S., & Tollenaere, M. (octobre 2010). Optimized return on inspection through smart-sampling [Communication écrite]. International Symposium on Semiconductor Manufacturing (ISSM 2010), Tokyo, Japan. Lien externe
