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Built-in self-test and self-repair architecture for defect-tolerant word-oriented large capacity memories

Nader Ghattas

Masters thesis (2004)

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Cite this document: Ghattas, N. (2004). Built-in self-test and self-repair architecture for defect-tolerant word-oriented large capacity memories (Masters thesis, École Polytechnique de Montréal). Retrieved from https://publications.polymtl.ca/7386/
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Abstract

Test algorithms and determining factors in choosing a repair architecture -- Global architecture and the self-testing function -- The self-repairing function and the SRAM block.

Uncontrolled Keywords

Ordinateurs -- Mémoires; Tolérance aux fautes (Informatique); Circuits intégrés -- Tolérance aux fautes

Open Access document in PolyPublie
Additional Information: Le fichier PDF de ce document a été produit par Bibliothèque et Archives Canada selon les termes du programme Thèses Canada https://canada.on.worldcat.org/oclc/63705050
Department: Département de génie électrique
Date Deposited: 04 Aug 2021 11:05
Last Modified: 25 Aug 2021 14:58
PolyPublie URL: https://publications.polymtl.ca/7386/

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