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Characterization of integrated MOS circuits under voltage stress and application to power conversion chains of electronic implants

Seyed Saeid Hashemi Aghcheh Body

Masters thesis (2004)

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Cite this document: Hashemi Aghcheh Body, S. S. (2004). Characterization of integrated MOS circuits under voltage stress and application to power conversion chains of electronic implants (Masters thesis, École Polytechnique de Montréal). Retrieved from https://publications.polymtl.ca/7315/
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Abstract

Motivation -- Research goals -- Thesis outline -- Power conversion chain for electronic implant -- Implant power-up techniques -- Constraints and limitations -- Conventional PCC's architecture -- Smart synchronous rectifier -- Smart synchronous rectifier versus classical diode rectifier -- New PCC architectures based on SSR -- High-efficient voltage multiplier -- Charge pump -- Single-stage voltage multiplier -- Voltage multiplier characteristics -- Power efficiency improvement -- Low-voltage application -- Multi-stage voltage multiplier -- Reliability challenges of CMOS under sub-micron regime -- Short channel effects -- Narrow-channel effects -- Subthreshold and leakage currents -- Hot carriers effects -- Punch-through -- Breakdown voltages -- Stress-induced measurement techniques -- Quantitative, simulation and measurement results -- Quantitative results for power conversion chains -- Simulation results for multi-stage voltage multiplier.

Uncontrolled Keywords

MOS (Électronique); Circuits intégrés

Open Access document in PolyPublie
Additional Information: Le fichier PDF de ce document a été produit par Bibliothèque et Archives Canada selon les termes du programme Thèses Canada https://canada.on.worldcat.org/oclc/58053253
Department: Département de génie électrique
Date Deposited: 04 Aug 2021 11:05
Last Modified: 25 Aug 2021 14:57
PolyPublie URL: https://publications.polymtl.ca/7315/

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