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MPEG-2 data encryption for transport over ATM/SONET and its clock generator

Beisong Liu

Masters thesis (2003)

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Cite this document: Liu, B. (2003). MPEG-2 data encryption for transport over ATM/SONET and its clock generator (Masters thesis, École Polytechnique de Montréal). Retrieved from https://publications.polymtl.ca/7133/
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Motivation -- Standards -- Surveying of analog and digital phase-locked loops -- Review of ADPLL technology -- Review of ATM/SONET interface -- Prospects -- Encrypted data transmission over ATM/SONET -- Description of the Data Transport Interface -- Overview of the physical Interface -- FIFO for Data Transport from MPEG-2 TS to ATM Cell -- Multi-High-frequency synchronous clock generator -- All digital delay locked loop and mirror delay approach -- Basic idea of the multiple-high-frequency SCG -- SCG architecture -- Implementation of the synchronous clock generator -- Chip characteristics and design flow -- ADDLL function for timing recovery -- The implementation of encryption DES algorithm -- Software-based logic verification -- Prototyping for DES algorithm using an FPGA -- Simulation result of the multiple-high-frequency SCG -- Testing of the fabricated ICDPMLIU chip -- Verification of the implementation of the DES algorithm.

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Additional Information: Le fichier PDF de ce document a été produit par Bibliothèque et Archives Canada selon les termes du programme Thèses Canada https://canada.on.worldcat.org/oclc/57166720
Department: Département de génie électrique
Date Deposited: 04 Aug 2021 11:05
Last Modified: 25 Aug 2021 14:57
PolyPublie URL: https://publications.polymtl.ca/7133/


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