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Analysis and characterisation of design for testability methodologies for bipolar current mode logics

Padmapriya Kumar

Masters thesis (2002)

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Cite this document: Kumar, P. (2002). Analysis and characterisation of design for testability methodologies for bipolar current mode logics (Masters thesis, École Polytechnique de Montréal). Retrieved from https://publications.polymtl.ca/7098/
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Abstract

Emitter coupled logic -- Bipolar CML gates -- VersArray technology -- The importance of testing -- Design for testability -- Significance of developing DFT methods for bipolar CML -- Faults and defects -- Fault modelling & defect modelling for bipolar CML -- Types of test -- Studied DFT techniques -- Bias alteration stress technique -- Test bench setup for characterising BAS technique -- Simulation results -- Observations -- Methods attempted to increase the usable range of bias voltages -- Simulations taking process variations into account -- Summary and conclusions on BAS testing -- Imbalance testing technique & stress accumulation -- Functionality of and gates -- Imbalance test technique -- Imbalance types and limits -- Analysis of stuck at behaviour observed in defect-free and gates -- Characterisation of ITT on one gate -- Overcoming stress accumulation -- Sensitivity analysis -- Overview of the proposed testing technique -- Deriving the sensitivity of V out to various parameters -- Environmental factors -- The testing of the test chip -- Device Array block -- Test control block -- Test pattern generation flow and the testing process -- Test pattern generation and the testing of the test chip.

Open Access document in PolyPublie
Additional Information: Le fichier PDF de ce document a été produit par Bibliothèque et Archives Canada selon les termes du programme Thèses Canada https://canada.on.worldcat.org/oclc/56683458
Department: Département de génie électrique
Date Deposited: 04 Aug 2021 11:05
Last Modified: 25 Aug 2021 14:57
PolyPublie URL: https://publications.polymtl.ca/7098/

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