An Area-Efficient and Bit-Width Configurable Carry-Save Adder Tree for Spiking Transformers

Chaoming Fang, Ziyang Shen, Fengshi Tian, Jie Yang and Mohamad Sawan

Paper (2025)

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Department:	Department of Electrical Engineering
Funders:	STI2030-Major Projects, Key Project of Westlake Institute for Optoelectronics
Grant number:	2022ZD0208805, 2023GD004
PolyPublie URL:	https://publications.polymtl.ca/66480/
Conference Title:	IEEE International Symposium on Circuits and Systems (ISCAS 2025)
Conference Location:	London, United Kingdom
Conference Date(s):	2025-05-25 - 2025-05-28
Publisher:	Institute of Electrical and Electronics Engineers
DOI:	10.1109/iscas56072.2025.11043823
Official URL:	https://doi.org/10.1109/iscas56072.2025.11043823
Date Deposited:	03 Jul 2025 10:18
Last Modified:	03 Jul 2025 10:18

Cite in APA 7:	Fang, C., Shen, Z., Tian, F., Yang, J., & Sawan, M. (2025, May). An Area-Efficient and Bit-Width Configurable Carry-Save Adder Tree for Spiking Transformers [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2025), London, United Kingdom. https://doi.org/10.1109/iscas56072.2025.11043823
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