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Abbasmollaei, M., Ould-Bachir, T., & Savaria, Y. (2025). HLSCAM: Fine-tuned HLS-based content addressable memory implementation for packet processing on FPGA. Electronics, 14(9), 1765 (22 pages). Disponible
Abbasmollaei, M., Ould-Bachir, T., & Savaria, Y. (2025). P4THLS: A Templated HLS Framework to Automate Efficient Mapping of P4 Data-Plane Applications to FPGAs. IEEE Access. Lien externe
Abbasmollaei, M., Ould-Bachir, T., & Savaria, Y. (2025). A Stateful Extension to P4THLS for Advanced Telemetry and Flow Control. Future Internet, 17(11), 530 (21 pages). Lien externe
Eddine Touati, D., Oukaira, A., Ali, M., Hassan, A., Savaria, Y., & Lakhssassi, A. (2025). Reliability Analysis Based on Cascaded-Foster Thermal Networks for Systems-in-Package (SiP). Results in Engineering, 27, 105965 (10 pages). Lien externe
Mashreghi-Moghadam, P., Ould-Bachir, T., & Savaria, Y. (2025). Templated and Overlay HW/SW Co-Optimization for Crossbar-Free P4 Deparser FPGA Architectures. Electronics, 14(24), 4850-4850. Lien externe
Moradi Chaleshtori, R., Saboohi, A., Faraji, A., Alireza Sadrossadat, S., Moftakharzadeh, A., & Savaria, Y. (2025). Long Short-Term Memory Neural Network Combined With a Hybrid-modular Clockwork Structure for Transient Modeling of Nonlinear Circuits. IEEE Access, 13, 107979-107993. Lien externe
Nojavan, A., Pontikakis, B., Boyer, F.-R., & Savaria, Y. (2025). 5G Fronthaul in Modular P4: eCPRI Protocol Processing and Precise BMv2 Timestamps for PTP-1588. IEEE Access, 1-1. Lien externe
Pabot, J., Amer, M., Savaria, Y., & Hassan, A. (2025). Integrated High-Voltage Bidirectional Protection Switches with Overcurrent Protection: Review and Design Guide. Electronics, 14(19), 3819 (19 pages). Lien externe
Rahmati, M., Boyer, F.-R., Pontikakis, B., David, J. P., & Savaria, Y. (2025). P4Muse: Enabling Modular P4 Programming via Compiler-Managed Code Merging Without Syntax Modifications. IEEE Access, 20 pages. Lien externe
Abdelfatah, M. M. S., Abuelnasr, A., Amer, M., Savaria, Y., & Hassan, A. (juin 2025). A Comparative Analysis of Off-Policy DRL Strategies for Analog Circuit Optimization: A Case Study on Bandgap References [Communication écrite]. 23rd IEEE Interregional NEWCAS Conference (NEWCAS 2025), Paris, France. Lien externe
Abuelnasr, A., Amer, M., Altoobaji, I., Hassan, A., & Savaria, Y. (novembre 2025). AI-Assisted Design of a Compact Voltage Monitoring System with a Millisecond-Delayed Fault Detection Circuit [Communication écrite]. 32nd International Conference on Electronics, Circuits and Systems (ICECS 2025), Marrakech, Morocco (4 pages). Lien externe
Amer, M., Abuelnasr, A., Hassan, A., & Savaria, Y. (novembre 2025). Comparative Thermal Analysis of Single vs. Arrayed Layouts for Integrated Power Transistors Using COMSOL [Communication écrite]. 32nd International Conference on Electronics, Circuits and Systems (ICECS 2025), Marrakech, Morocco (4 pages). Lien externe
Posso, J., Bois, G., & Savaria, Y. (2025). Dynamic-Spacecraft Pose Estimation Dataset (D-SPEED) [Ensemble de données]. Lien externe
