 | Monter d'un niveau |
Condo, C., Giard, P., Leduc-Primeau, F., Sarkis, G., & Gross, W. J. (2018). A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(4), 1420-1431. Lien externe
Dupraz, E., Leduc-Primeau, F., & Gagnon, F. (décembre 2018). Low-Latency LDPC Decoding Achieved by Code and Architecture Co-Design [Communication écrite]. International Symposium on Turbo Codes & Iterative Information Processing (ISTC 2018), Hong Kong, Chine. Lien externe
Leduc-Primeau, F., Kschischang, F. R., & Gross, W. J. (2018). Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations. IEEE Transactions on Communications, 66(3), 932-946. Lien externe
Nadal, J., Leduc-Primeau, F., Nour, C. A., & Baghdadi, A. (mai 2018). A Block FBMC Receiver Designed for Short Filters [Communication écrite]. IEEE International Conference on Communications (ICC 2018), Kansas City, MO, USA (6 pages). Lien externe
