Elsa Dupraz, François Leduc-Primeau
and François Gagnon
Paper (2018)
Document published while its authors were not affiliated with Polytechnique Montréal
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| Research Center: | GR2M - Microelectronics and Microsystems Research Group |
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| PolyPublie URL: | https://publications.polymtl.ca/41623/ |
| Conference Title: | International Symposium on Turbo Codes & Iterative Information Processing (ISTC 2018) |
| Conference Location: | Hong Kong, Chine |
| Conference Date(s): | 2018-12-03 - 2018-12-07 |
| Publisher: | Institute of Electrical and Electronics Engineers |
| DOI: | 10.1109/istc.2018.8625276 |
| Official URL: | https://doi.org/10.1109/istc.2018.8625276 |
| Date Deposited: | 18 Apr 2023 15:03 |
| Last Modified: | 25 Sep 2024 16:27 |
| Cite in APA 7: | Dupraz, E., Leduc-Primeau, F., & Gagnon, F. (2018, December). Low-Latency LDPC Decoding Achieved by Code and Architecture Co-Design [Paper]. International Symposium on Turbo Codes & Iterative Information Processing (ISTC 2018), Hong Kong, Chine. https://doi.org/10.1109/istc.2018.8625276 |
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