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Ahmadi, M., Vakili, S., Langlois, J. M. P., & Gross, W. J. (juin 2018). Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy [Communication écrite]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. Lien externe
Ardakani, A., Condo, C., Ahmadi, M., & Gross, W. J. (2018). An architecture to accelerate convolution in deep neural networks. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(4), 1349-1362. Lien externe
Condo, C., Giard, P., Leduc-Primeau, F., Sarkis, G., & Gross, W. J. (2018). A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(4), 1420-1431. Lien externe
Leduc-Primeau, F., Kschischang, F. R., & Gross, W. J. (2018). Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations. IEEE Transactions on Communications, 66(3), 932-946. Lien externe
