 | Monter d'un niveau |
Bouchebaba, Y., Bensoudane, E., Lavigueur, B., Paulin, P., & Nicolescu, G. (juillet 2007). Two-level tiling for MPSoC architecture [Communication écrite]. International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007), Montréal, QC, Canada. Lien externe
Bouchebaba, Y., Girodias, B., Nicolescu, G., Aboulhamid, E. M., Lavigueur, B., & Paulin, P. (2007). MPSoC memory optimization using program transformation. ACM Transactions on Design Automation of Electronic Systems, 12(4), 43-43. Lien externe
Bouchebaba, Y., Girodias, B., Nicolescu, G., Coelho, F., & Aboulhamid, E. M. (2007). Buffer and register allocation for memory space optimization. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 49(1), 123-138. Présentée à IEEE 15th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2004), Galveston, Texas. Lien externe
Bouchhima, F., Nicolescu, G., Aboulhamid, E. M., & Abid, M. (2007). Generic Discrete-Continuous Simulation Model for Accurate Validation in Heterogeneous Systems Design. Microelectronics Journal, 38(6-7), 805-815. Lien externe
Briere, M., Girodias, B., Bouchebaba, Y., Nicolescu, G., Mieyeville, F., Gaffiot, F., & O'Connor, I. (avril 2007). System level assessment of an optical NoC in an MPSoC platform [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice Acropolis, France. Lien externe
Briere, M., Girodias, B., Bouchebaba, Y., Nicolescu, G., Mieyeville, F., Gafflot, F., & O'Connor, I. (août 2007). Architectural exploration of optical and electrical interconnects in MPSoC [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montreal, QC, Canada (4 pages). Lien externe
Gheorghe, L., Bouchhima, F., Nicolescu, G., & Abid, M. (2007). Anatomy of a continuous/discrete system execution model for timed execution of heterogeneous systems. Dans Global Specification and Validation of Embedded Systems: Integrating Heterogeneous Components (p. 75-108). Lien externe
Hireche, N., Langlois, J. M. P., & Nicolescu, G. (août 2007). A systolic array for sequence comparison based on two logic levels processing element [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. Lien externe
Lapalme, J., Aboulhamid, E. M., Nicolescu, G., & Rousseau, F. (2007). Separating Modeling and Simulation Aspects in Hardware/Software Framework-Based Modeling Languages. Arabian Journal for Science and Engineering, 32(2C), 41-60. Lien externe
Nicolescu, G., & Jerraya, A. A. (2007). Anatomy of a hardware/software execution model in heterogeneous systems. Dans Global Specification and Validation of Embedded Systems: Integrating Heterogeneous Components (p. 59-74). Lien externe
Nicolescu, G., & Jerraya, A. A. (2007). Heterogeneous systems validation based on execution models. Dans Global Specification and Validation of Embedded Systems: Integrating Heterogeneous Components (p. 47-57). Lien externe
Nicolescu, G., & Jerraya, A. A. (2007). Methodology for heterogeneous systems validation. Dans Global Specification and Validation of Embedded Systems: Integrating Heterogeneous Components (p. 109-145). Lien externe
