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Epassa, H. G., Boyer, F.-R., & Savaria, Y. (mai 2005). Implementation of a Cycle by Cycle Variable Speed Processor [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Pontikakis, B., Boyer, F.-R., & Savaria, Y. (juillet 2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period [Communication écrite]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. Lien externe
