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Antaki, B., Savaria, Y., Adham, S., Xiong, N., Borrione, D., & Ernst, R. (mars 1999). Design for testability method for CML digital circuits [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 1999), Munich, Germany. Lien externe
Bosi, B., Bois, G., & Savaria, Y. (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3), 299-308. Lien externe
Calbaza, D. E., & Savaria, Y. (mai 1999). Jitter model of direct digital synthesis clock generators [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. Lien externe
Cousineau, C., Laperle, F., Savaria, Y., Pocek, K. L., & Arnold, J. M. (avril 1999). Design of a JTAG based run time reconfigurable system [Communication écrite]. 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA. Lien externe
Donfack, C., Sawan, M., & Savaria, Y. (janvier 1999). Efficient monitoring of electrodes-nerve contacts during FNS of the bladder [Communication écrite]. 4th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 1999), Sendai, Japon. Non disponible
Jiang, Y., Tang, Y., Wang, Y., & Savaria, Y. (mai 1999). Evaluating the ouptput probability of boolean functions without floating point operations [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1999), Edmonton, AB, Canada. Lien externe
Jin, Z.-F., Laurin, J.-J., & Savaria, Y. New approach to analyze interconnect delays in RC wire models [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1999). Non disponible
Lavoie, P., Crespo, J. F., & Savaria, Y. (1999). Generalization, Discrimination, and Multiple Categorization Using Adaptive Resonance Theory. IEEE Transactions on Neural Networks, 10(4), 757-767. Lien externe
Le Chapelain, B., Mechain, A., Savaria, Y., & Bois, G. (mai 1999). Development of a high performance TSPC library for implementation of large digital building blocks [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. Lien externe
Nekili, M., Savaria, Y., & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84. Lien externe
Nsame, P., & Savaria, Y. (janvier 1999). Virtualising on-chip bus interfaces for improved embedded processor system performance [Communication écrite]. IFIP International Workshop on IP Based Synthesis and System Design, Grenoble, France. Non disponible
Antaki, B., Savaria, Y., Adham, S., Xiong, N., Borrione, D., & Ernst, R. (mars 1999). Design for testability method for CML digital circuits [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 1999), Munich, Germany. Lien externe
Bosi, B., Bois, G., & Savaria, Y. (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3), 299-308. Lien externe
Calbaza, D. E., & Savaria, Y. (mai 1999). Jitter model of direct digital synthesis clock generators [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. Lien externe
Cousineau, C., Laperle, F., Savaria, Y., Pocek, K. L., & Arnold, J. M. (avril 1999). Design of a JTAG based run time reconfigurable system [Communication écrite]. 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA. Lien externe
Donfack, C., Sawan, M., & Savaria, Y. (janvier 1999). Efficient monitoring of electrodes-nerve contacts during FNS of the bladder [Communication écrite]. 4th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 1999), Sendai, Japon. Non disponible
Jiang, Y., Tang, Y., Wang, Y., & Savaria, Y. (mai 1999). Evaluating the ouptput probability of boolean functions without floating point operations [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1999), Edmonton, AB, Canada. Lien externe
Jin, Z.-F., Laurin, J.-J., & Savaria, Y. New approach to analyze interconnect delays in RC wire models [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1999). Non disponible
Lavoie, P., Crespo, J. F., & Savaria, Y. (1999). Generalization, Discrimination, and Multiple Categorization Using Adaptive Resonance Theory. IEEE Transactions on Neural Networks, 10(4), 757-767. Lien externe
Le Chapelain, B., Mechain, A., Savaria, Y., & Bois, G. (mai 1999). Development of a high performance TSPC library for implementation of large digital building blocks [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. Lien externe
Nekili, M., Savaria, Y., & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84. Lien externe
Nsame, P., & Savaria, Y. (janvier 1999). Virtualising on-chip bus interfaces for improved embedded processor system performance [Communication écrite]. IFIP International Workshop on IP Based Synthesis and System Design, Grenoble, France. Non disponible
