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BenHamida, N., & Kamińska, B. (mai 1994). High level synthesis with testability constraints [Communication écrite]. IEEE International Symposium on Circuits and Systems - ISCAS '94, London, UK. Lien externe
BenHamida, N., & Kamińska, B. (janvier 1994). Multiple fault testing in analog circuits [Communication écrite]. 7th International Conference on VLSI Design, Calcutta, India. Lien externe
BenHamida, N., Kamińska, B., & Savaria, Y. (mai 1994). Pseudo-random vector compaction for sequential testability [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe
