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Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M.-A., & Morawski, R. Z. (mai 1993). An integrated structure for Kalman-filter-based measurand reconstruction architecture and design [Communication écrite]. Instrumentation and Measurement Technology Conference 1993, Irvine, CA, USA. Lien externe
Blaquière, Y., Dagenais, M., & Savaria, Y. (février 1993). A new accurate and hierarchical timing analysis approach [Communication écrite]. European Conference on Design Automation (EDAC 1993), Paris, France. Lien externe
Crépeau, J., Thibeault, C., & Savaria, Y. (octobre 1993). Some results on yield and local design rule relaxation [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1993), Venice, Italy. Lien externe
Dahmani, A., Savaria, Y., & Kamińska, B. (février 1993). ML-Germinal: A new heuristic standard cell placement algorithm [Communication écrite]. European Conference on Design Automation (EDAC 1993), Paris, France. Lien externe
Guterman, A. J., Savaria, Y., & Dagenais, M. (avril 1993). On the diagnosability of DNMR testing [Communication écrite]. 3rd European Test Conference, Rotterdam, Netherlands. Lien externe
Savaria, Y., & Thibeault, C. (août 1993). An inexpensive method of detecting localised parametric defects in static RAM [Communication écrite]. IEEE International Workshop on Memory Testing (MT 1993), San Jose, CA, United states. Lien externe
Serra, M., McLeod, B. A., Sorbin, B., Turner, L., & Savaria, Y. (1993). New advances in microelectronics education: a Canadian model. IEEE Transactions on Education, 36(1), 141-147. Lien externe
Vinh, H. T., Audet, D., & Savaria, Y. (septembre 1993). Performance models for optimizing a hierarchical-bus multiprocessor architecture [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1993), Vancouver, BC, Canada. Lien externe
