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Thibeault, C., & Savaria, Y. (novembre 1992). Comparing results from defect-tolerant yield models [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1992), Dallas, TX, United states. Lien externe
Thibeault, C., Savaria, Y., & Houle, J. L. (1992). Heuristic prediction of the optimum number of spares in defect-tolerant integrated circuits. Journal of Circuits Systems and Computers, 02(02), 81-100. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1992). Test quality of hierarchical defect-tolerant integrated circuits. Journal of Electronic Testing, 3(1), 93-102. Lien externe
