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Audet, D., Savaria, Y., & Houle, J.-L. (1992). Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources. Parallel Computing, 18(2), 149-167. Lien externe
Belabbes, N., Guterman, A., Savaria, Y., & Dagenais, M. (mai 1992). Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. Lien externe
Dahmani, A., Savaria, Y., & Kaminska, B. (mai 1992). Standard cell placement with Dynamic Clouds method [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. Lien externe
Nekili, M., & Savaria, Y. (mai 1992). Optimal methods of driving interconnections in VLSI circuits [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. Lien externe
Thibeault, C., & Savaria, Y. (novembre 1992). Comparing results from defect-tolerant yield models [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1992), Dallas, TX, United states. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1992). Test quality of hierarchical defect-tolerant integrated circuits. Journal of Electronic Testing, 3(1), 93-102. Lien externe
